alarm.vhd

来自「实现60进制的计数」· VHDL 代码 · 共 31 行

--alarm
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alarm is 
port(mh,m,sh,s:in std_logic_vector(3 downto 0);
     clk1,clk2,co:in std_logic;
     q:out std_logic);
end alarm;
architecture rtl of alarm is
signal q1:std_logic;
begin
process(mh,m,sh,s,co)
begin
    if co='1' then
    if mh="0101" and m="1001" then
     if sh="0101" and (s(2)='1' or s(3)='1') then
         q1<=clk1;
      end if;
   elsif mh="0000" and m="0000" then
      if sh="0000" and s="0000" then
     q1<=clk2;
      end if;
   end if;
   end if;
end process;
q<=q1;
end rtl;