t_mux.vhd

来自「实现60进制的计数」· VHDL 代码 · 共 20 行

--t_mux
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity t_mux is
  port(a,b,sel:in std_logic;
       q:out std_logic);
end t_mux;
architecture rtl of t_mux is
 begin
process(sel,a,b)
   begin
 if sel='0' then
   q<=a;
 end if;
 if sel='1' then
   q<=b;
 end if;
end process;
end rtl;