verilog.java

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

	 * to that text to the output file.  Returns true if anything
	 * was found.
	 */
	private boolean includeTypedCode(Cell cell, Variable.Key verilogkey, String descript)
	{
		// write out any directly-typed Verilog code
		boolean first = true;
		for(Iterator<NodeInst> it = cell.getNodes(); it.hasNext(); )
		{
			NodeInst ni = it.next();
			if (ni.getProto() != Generic.tech().invisiblePinNode) continue;
			Variable var = ni.getVar(verilogkey);
			if (var == null) continue;
			if (!var.isDisplay()) continue;
			Object obj = var.getObject();
			if (!(obj instanceof String) && !(obj instanceof String [])) continue;
			if (first)
			{
				first = false;
				printWriter.println("  /* user-specified Verilog " + descript + " */");
			}
			if (obj instanceof String)
			{
            	String tmp = replaceVarInString((String)obj, cell);
            	printWriter.println("  " + tmp);
				// printWriter.println("  " + (String)obj);
			} else
			{
				String [] stringArray = (String [])obj;
				int len = stringArray.length;
				for(int i=0; i<len; i++) {
                	String tmp = replaceVarInString(stringArray[i], cell);
                	printWriter.println("  " + tmp);
					// printWriter.println("  " + stringArray[i]);
                }
			}
		}
		if (!first) printWriter.println();
		return first;
	}

	private StringBuffer sim_verDeclarationLine;
	private int sim_verdeclarationprefix;

	/**
	 * Method to initialize the collection of signal names in a declaration.
	 * The declaration starts with the string "header".
	 */
	private void initDeclaration(String header)
	{
		sim_verDeclarationLine = new StringBuffer();
		sim_verDeclarationLine.append(header);
		sim_verdeclarationprefix = header.length();
	}

	/**
	 * Method to add "signame" to the collection of signal names in a declaration.
	 */
	private void addDeclaration(String signame)
	{
		if (sim_verDeclarationLine.length() + signame.length() + 3 > MAXDECLARATIONWIDTH)
		{
			printWriter.println(sim_verDeclarationLine.toString() + ";");
			sim_verDeclarationLine.delete(sim_verdeclarationprefix, sim_verDeclarationLine.length());
		}
		if (sim_verDeclarationLine.length() != sim_verdeclarationprefix)
			sim_verDeclarationLine.append(",");
		sim_verDeclarationLine.append(" " + signame);
	}

	/**
	 * Method to terminate the collection of signal names in a declaration
	 * and write the declaration to the Verilog file.
	 */
	private void termDeclaration()
	{
		printWriter.println(sim_verDeclarationLine.toString() + ";");
	}

	/**
	 * Method to adjust name "p" and return the string.
	 * This code removes all index indicators and other special characters, turning
	 * them into "_".
	 */
	private String nameNoIndices(String p)
	{
		StringBuffer sb = new StringBuffer();
		if (TextUtils.isDigit(p.charAt(0))) sb.append('_');
		for(int i=0; i<p.length(); i++)
		{
			char chr = p.charAt(i);
			if (!TextUtils.isLetterOrDigit(chr) && chr != '_' && chr != '$') chr = '_';
			sb.append(chr);
		}
		return sb.toString();
	}

	/****************************** SUBCLASSED METHODS FOR THE TOPOLOGY ANALYZER ******************************/

	/**
	 * Method to adjust a cell name to be safe for Verilog output.
	 * @param name the cell name.
	 * @return the name, adjusted for Verilog output.
	 */
	protected String getSafeCellName(String name)
	{
		String n = getSafeNetName(name, false);
		// [ and ] are not allowed in cell names
		return n.replaceAll("[\\[\\]]", "_");
	}

	/** Method to return the proper name of Power */
	protected String getPowerName(Network net) { return "vdd"; }

	/** Method to return the proper name of Ground */
	protected String getGroundName(Network net) { return "gnd"; }

	/** Method to return the proper name of a Global signal */
	protected String getGlobalName(Global glob) { return "glbl." + glob.getName(); }

	/** Method to report that export names DO take precedence over
	 * arc names when determining the name of the network. */
	protected boolean isNetworksUseExportedNames() { return true; }

	/** Method to report that library names ARE always prepended to cell names. */
	protected boolean isLibraryNameAlwaysAddedToCellName() { return true; }

	/** Method to report that aggregate names (busses) ARE used. */
	protected boolean isAggregateNamesSupported() { return true; }

	/** Abstract method to decide whether aggregate names (busses) can have gaps in their ranges. */
	protected boolean isAggregateNameGapsSupported() { return true; }

	/** Method to report whether input and output names are separated. */
	protected boolean isSeparateInputAndOutput() { return true; }

	/** Abstract method to decide whether netlister is case-sensitive (Verilog) or not (Spice). */
	protected boolean isCaseSensitive() { return true; }

	/**
	 * Method to adjust a network name to be safe for Verilog output.
	 * Verilog does permit a digit in the first location; prepend a "_" if found.
	 * Verilog only permits the "_" and "$" characters: all others are converted to "_".
	 * Verilog does not permit nonnumeric indices, so "P[A]" is converted to "P_A_"
	 * Verilog does not permit multidimensional arrays, so "P[1][2]" is converted to "P_1_[2]"
	 *   and "P[1][T]" is converted to "P_1__T_"
	 * @param bus true if this is a bus name.
	 */
	protected String getSafeNetName(String name, boolean bus)
	{
		// simple names are trivially accepted as is
		boolean allAlnum = true;
		int len = name.length();
		if (len == 0) return name;
		int openSquareCount = 0;
		int openSquarePos = 0;
		for(int i=0; i<len; i++)
		{
			char chr = name.charAt(i);
			if (chr == '[') { openSquareCount++;   openSquarePos = i; }
			if (!TextUtils.isLetterOrDigit(chr)) allAlnum = false;
			if (i == 0 && TextUtils.isDigit(chr)) allAlnum = false;
		}
		if (!allAlnum || !Character.isLetter(name.charAt(0)))
		{
			// if there are indexed values, make sure they are numeric
			if (openSquareCount == 1)
			{
				if (openSquarePos+1 >= name.length() ||
					!Character.isDigit(name.charAt(openSquarePos+1))) openSquareCount = 0;
			}
			if (bus) openSquareCount = 0;

			StringBuffer sb = new StringBuffer();
			for(int t=0; t<name.length(); t++)
			{
				char chr = name.charAt(t);
				if (chr == '[' || chr == ']')
				{
					if (openSquareCount == 1) sb.append(chr); else
					{
						sb.append('_');

						// merge two underscores into one
//						if (t+1 < name.length() && chr == ']' && name.charAt(t+1) == '[') t++;
					}
				} else
				{
					if (t == 0 && TextUtils.isDigit(chr)) sb.append('_');
					if (TextUtils.isLetterOrDigit(chr) || chr == '$')
						sb.append(chr); else
							sb.append('_');
				}
			}
			name = sb.toString();
		}

		// make sure it isn't a reserved word
		if (reservedWords.contains(name)) name = "_" + name;

		return name;
	}

	/** Tell the Hierarchy enumerator how to short resistors */
	@Override
	protected Netlist.ShortResistors getShortResistors() { return Netlist.ShortResistors.PARASITIC; }

	/**
	 * Method to tell whether the topological analysis should mangle cell names that are parameterized.
	 */
	protected boolean canParameterizeNames() {
		if (Simulation.getVerilogStopAtStandardCells())
			return false;

		// Check user preference
		if (Simulation.getVerilogParameterizeModuleNames()) return true;
		return false;
	}

	private static final String [] verilogGates = new String [] {
		"and",
		"nand",
		"or",
		"nor",
		"xor",
		"xnor",
		"buf",
		"bufif0",
		"bufif1",
		"not",
		"notif0",
		"notif1",
		"pulldown",
		"pullup",
		"nmos",
		"rnmos",
		"pmos",
		"rpmos",
		"cmos",
		"rcmos",
		"tran",
		"rtran",
		"tranif0",
		"rtranif0",
		"tranif1",
		"rtranif1",
	};

	/**
	 * Perform some checks on parsed Verilog data, including the
	 * check that module is defined for the cell it is replacing.
	 * Some checks are different depending upon if the source is
	 * a Verilog View or an included external file.
	 * @param data the parsed Verilog data
	 * @param cell the cell to be replaced (must be verilog view if replacing Verilog View)
	 * @param includeFile the included file (null if replacing Verilog View)
	 * @return false if there was an error
	 */
	private boolean checkIncludedData(VerilogData data, Cell cell, String includeFile) {
		// make sure there is module for current cell
		Collection<VerilogData.VerilogModule> modules = data.getModules();
		VerilogData.VerilogModule main = null, alternative = null;
		for (VerilogData.VerilogModule mod : modules) {
			if (mod.getName().equals(getVerilogName(cell)))
				main = mod;
			else {
				Cell.CellGroup grp = cell.getCellGroup(); // if cell group is available
				if (grp != null && mod.getName().equals(grp.getName()))
					alternative = mod;
			}
		}
		if (main == null) main = alternative;
		if (main == null) {
			System.out.println("Error! Expected Verilog module definition '"+getVerilogName(cell)+
			" in Verilog View: "+cell.libDescribe());
			return false;
		}
        if (main.isPrimitive())
            definedPrimitives.put(cell, main);

		String source = includeFile == null ? "Verilog View for "+cell.libDescribe() :
			"Include file: "+includeFile;
		// check that modules have not already been defined
		for (VerilogData.VerilogModule mod : modules) {
			String prevSource = definedModules.get(mod.getName());
			if (mod.isValid()) {
				if (prevSource != null) {
					System.out.println("Error, module "+mod.getName()+" already defined from: "+prevSource);
				}
				else
					definedModules.put(mod.getName(), source);
			}
		}

		// make sure ports for module match ports for cell
//		Collection<VerilogData.VerilogPort> ports = main.getPorts();
		// not sure how to do this right now

		// check for undefined instances, search libraries for them
		for (VerilogData.VerilogModule mod : modules) {
			for (VerilogData.VerilogInstance inst : mod.getInstances()) {
				VerilogData.VerilogModule instMod = inst.getModule();
				if (instMod.isValid())
					continue;	   // found in file, continue
				// check if primitive
				boolean primitiveGate = false;
				for (String s : verilogGates) {
					if (s.equals(instMod.getName().toLowerCase())) {
						primitiveGate = true;
						break;
					}
				}
				if (primitiveGate) continue;

				// undefined, look in modules already written
				String moduleName = instMod.getName();
				String found = definedModules.get(moduleName);
				if (found == null && includeFile == null) {
					// search libraries for it
					Cell missingCell = findCell(moduleName, View.VERILOG);
					if (missingCell == null) {
						System.out.println("Error: Undefined reference to module "+moduleName+", and no matching cell found");
						continue;
					}
					// hmm...name map might be wrong at for this new enumeration
					System.out.println("Info: Netlisting cell "+missingCell.libDescribe()+" as instanced in: "+source);
					HierarchyEnumerator.enumerateCell(missingCell, VarContext.globalContext,
						new Visitor(this), getShortResistors());
				}
			}
		}
		return true;
	}

	/**
	 * Get the Verilog-style name for a cell.
	 * @param cell the cell to name.
	 * @return the name of the cell.
	 */
	private String getVerilogName(Cell cell) {
        // this should mirror the code in parameterizedName(), minus the parameter stuff
        String uniqueCellName = getUniqueCellName(cell);
        if (uniqueCellName != null) return uniqueCellName;
        // otherwise, use old code
        String safeCellName = getSafeCellName(cell.getName());
		if (!safeCellName.startsWith("_")) safeCellName = "__" + safeCellName;
		return cell.getLibrary().getName() + safeCellName;
    }

	/**
	 * Find a cell corresponding to the Verilog-style name
	 * of a cell. See
	 * {@link Verilog#getVerilogName(com.sun.electric.database.hierarchy.Cell)}.
	 * @param verilogName the Verilog-style name of the cell
	 * @param preferredView the preferred cell view. Schematic if null.
	 * @return the cell, or null if not found
	 */
	public static Cell findCell(String verilogName, View preferredView) {
		String [] parts = verilogName.split("__");
		if (parts.length != 2) {
			//System.out.println("Invalid Verilog-style module name: "+verilogName);
			return null;
		}
		Library lib = Library.findLibrary(parts[0]);
		if (lib == null) {
			System.out.println("Cannot find library "+parts[0]+" for Verilog-style module name: "+verilogName);
			return null;
		}
		if (preferredView == null) preferredView = View.SCHEMATIC;
		Cell cell = lib.findNodeProto(parts[1]);
		if (cell == null) {
			System.out.println("Cannot find Cell "+parts[1]+" in Library "+parts[0]+" for Verilog-style module name: "+verilogName);
			return null;
		}
		Cell preferred = cell.otherView(preferredView);
		if (pr