verilog.java

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

						break;
					}
					if (netList.sameNetwork(no, pp, no, cas2.getExport())) {
						// this will be true if there are two exports connected together
						// in the subcell, and we are searching for the export name that is not used.
						cas = cas2;
						break;
					}
				}
			} else {
				// maybe it is a single bit in an bussed export
				for (Iterator<PortProto> it = no.getProto().getPorts(); it.hasNext(); ) {
					PortProto ppcheck = it.next();
					for (int i=0; i<ppcheck.getNameKey().busWidth(); i++) {
						if (paramName.equals(ppcheck.getNameKey().subname(i).toString())) {
							Network net = netList.getNetwork(no, ppcheck, i);
							netcs = cni.getCellSignal(net);
							break;
						}
					}
				}
			}

			if (cas != null) {
				// this code is copied from instantiated
				if (cas.getLowIndex() > cas.getHighIndex())
				{
					// single signal
					Network net = netList.getNetwork(no, pp, cas.getExportIndex());
					CellSignal cs = cni.getCellSignal(net);
					infstr.append(getSignalName(cs));
				} else
				{
					int total = cas.getNumSignals();
					CellSignal [] outerSignalList = new CellSignal[total];
					for(int j=0; j<total; j++)
					{
						CellSignal cInnerSig = cas.getSignal(j);
						Network net = netList.getNetwork(no, cas.getExport(), cInnerSig.getExportIndex());
						outerSignalList[j] = cni.getCellSignal(net);
					}
					writeBus(outerSignalList, total, cas.isDescending(),
						null, cni.getPowerNet(), cni.getGroundNet(), infstr);
				}
			} else if (netcs != null) {
				infstr.append(getSignalName(netcs));
			} else if (paramName.equalsIgnoreCase("node_name"))
			{
				infstr.append(getSafeNetName(no.getName(), true));
			} else
			{
				// no port name found, look for variable name
				Variable var = null;
				Variable.Key varKey = Variable.findKey("ATTR_" + paramName);
				if (varKey != null) {
					var = no.getParameterOrVariable(varKey);
				}
				if (var == null) infstr.append("??"); else
				{
					infstr.append(context.evalVar(var));
				}
			}
		}
		infstr.append("\n");
		writeWidthLimited(infstr.toString());
	}

    /**
     * writeDefparam is a specialized version of writeTemplate.  This function will
     * take a Electric Variable (Attribute) and write it out as a parameter.
     * @param line
     * @param no
     * @param cni
     * @param context
     * @return
     */
    private String writeDefparam(String line, Nodable no, VarContext context)
    {
        // special case for Verilog defparams
        StringBuffer infstr = new StringBuffer();
        // Setup a standard template for defparams
        infstr.append("  defparam ");
        // Get the nodes instance name
        infstr.append(getSafeNetName(no.getName(), true));
        infstr.append(".");
        // Prepend whatever text is on the line, assuming it is a a variable per line
        // Garbage will be generated otherwise
        for(int pt = 0; pt < line.length(); pt++)
        {
            char chr = line.charAt(pt);
            if (chr != '$' || pt+1 >= line.length() || line.charAt(pt+1) != '(')
            {
                // process normal character
                infstr.append(chr);
                continue;
            }

            int startpt = pt + 2;
            for(pt = startpt; pt < line.length(); pt++)
                if (line.charAt(pt) == ')') break;
            String paramName = line.substring(startpt, pt);
            // Check the current parameter value against the default parameter value
			// only overwrite if they are different.
            if (!(no.getProto() instanceof Cell))
            {
            	System.out.println("Illegal attempt to replace a variable.");
            	return "";
            }
			String defaultValue = replaceVariable(paramName, (Cell) no.getProto());
            String paramValue = replaceVariable(paramName, no, context);

            if (paramValue == "" || paramValue.equals(defaultValue)) return "";
        	infstr.append(paramName);
        	infstr.append(" = ");
            infstr.append(paramValue);
        	infstr.append(";");
        }
        infstr.append("\n");
        // writeWidthLimited(infstr.toString());
        return infstr.toString();
    }

    /**
	 * replaceVariable - Replace Electric variables (attributes) with their
	 * values on instances of a cell. Given that left and right parens are not
	 * valid characters in Verilog identifiers, any Verilog code that matches
	 * $([a-zA-Z0-9_$]*) is not a valid sequence. This allows us to extract any
	 * electric variable and replace it with the attribute value.
	 * Additionally, search the value of the Electric variable for a nested
	 * variable and replace that as well.
	 * Added for ArchGen Plugin - BVE
	 * 
	 * @param line
	 * @param no
	 * @param context
	 * @return
	 */
    private String replaceVariable(String varName, Nodable no, VarContext context)
    {
    	// FIXIT - BVE should this be getSafeCellName
    	if (varName.equalsIgnoreCase("node_name"))
    		return getSafeNetName(no.getName(), true);

		// look for variable name
		Variable var = null;
		Variable.Key varKey = Variable.findKey("ATTR_" + varName);
		if (varKey != null)
		{
			var = no.getVar(varKey);
			if (var == null) var = no.getParameter(varKey);
        }
		if (var == null) return ""; 
		String val = String.valueOf(context.evalVar(var));

		// Semi-recursive call to search the value of a variable for a nested variable.
		return replaceVarInString(val, no.getParent());
    }

    /**
	 * replaceVariable - Replace Electric variables (attributes) with their
	 * values on definitions of a cell. Given that left and right parens are not
	 * valid characters in Verilog identifiers, any verilog code that matches
	 * $([a-zA-Z0-9_$]*) is not a valid sequence. This allows us to extract any
	 * electric variable and replace it with the attribute value.
	 * Added for ArchGen Plugin - BVE
	 * 
	 * @param line
	 * @param cell
	 * @return
	 */
    private String replaceVariable(String varName, Cell cell)
    {
    	// FIXIT - BVE should this be getSafeCellName
    	if (varName.equalsIgnoreCase("node_name"))
    		return getSafeNetName(cell.getName(), true);

    	// look for variable name
		Variable var = null;
		Variable.Key varKey = Variable.findKey("ATTR_" + varName);
		if (varKey != null) {
			var = cell.getVar(varKey);
			if (var == null) var = cell.getParameter(varKey);
        }
		if (var == null) return ""; 

		// Copied this code from VarContext.java - evalVarRecurse
        CodeExpression.Code code = var.getCode();
        Object value = var.getObject();

        if ((code == CodeExpression.Code.JAVA) ||
        	(code == CodeExpression.Code.TCL) ||
        	(code == CodeExpression.Code.SPICE)) return "";

        return String.valueOf(value);
    }

    /**
	 * replaceVarInString will search a string and replace any electric variable
	 * with its attribute or parameter value, if it has one.
	 * Added for ArchGen Plugin - BVE
	 * 
	 * @param line
	 * @param cell
	 * @return
	 */
    private String replaceVarInString(String line, Cell cell)
    {
        StringBuffer infstr = new StringBuffer();
        // Search the line for any electric variables
        for(int pt = 0; pt < line.length(); pt++)
        {
            char chr = line.charAt(pt);
            if (chr != '$' || pt+1 >= line.length() || line.charAt(pt+1) != '(')
            {
                // process normal character
                infstr.append(chr);
                continue;
            }

            int startpt = pt + 2;
            for(pt = startpt; pt < line.length(); pt++)
                if (line.charAt(pt) == ')') break;
            String paramName = line.substring(startpt, pt);
            String paramValue = replaceVariable(paramName, cell);

            // If the parameter doesn't have a value, then look in the bus parameters
            if (paramValue != "") {
            	infstr.append(paramValue);
            }else {
            	paramValue = BusParameters.replaceBusParameterInt("$("+paramName+")");
                // If the parameter isn't a bus parameter, then just leave the paramName
            	if (paramValue != "") {
            		infstr.append(paramValue);
            	} else
            	{
            		infstr.append("$(");
            		infstr.append(paramName);
            		infstr.append(")");
            	}
            }
        }
        return infstr.toString();
    }

	/**
	 * Method to add a bus of signals named "name" to the infinite string "infstr".  If "name" is zero,
	 * do not include the ".NAME()" wrapper.  The signals are in "outerSignalList" and range in index from
	 * "lowindex" to "highindex".  They are described by a bus with characteristic "tempval"
	 * (low bit is on if the bus descends).  Any unconnected networks can be numbered starting at
	 * "*unconnectednet".  The power and grounds nets are "pwrnet" and "gndnet".
	 */
	private void writeBus(CellSignal [] outerSignalList, int total, boolean descending,
						String name, Network pwrNet, Network gndNet, StringBuffer infstr)
	{
		// array signal: see if it gets split out
		boolean breakBus = false;

		// bus cannot have pwr/gnd, must be connected
		int numExported = 0, numInternal = 0;
		for(int j=0; j<total; j++)
		{
			CellSignal cs = outerSignalList[j];
			CellAggregateSignal cas = cs.getAggregateSignal();
			if (cas != null && cas.getIndices() != null) { breakBus = true;   break; }
			if (cs.isPower() || cs.isGround()) { breakBus = true;   break; }
			if (cs.isExported()) numExported++; else
				numInternal++;
		}

		// must be all exported or all internal, not a mix
		if (numExported > 0 && numInternal > 0) breakBus = true;

		if (!breakBus)
		{
			// see if all of the nets on this bus are distinct
			int j = 1;
			for( ; j<total; j++)
			{
				CellSignal cs = outerSignalList[j];
				int k = 0;
				for( ; k<j; k++)
				{
					CellSignal oCs = outerSignalList[k];
					if (cs == oCs) break;
				}
				if (k < j) break;
			}
			if (j < total) breakBus = true; else
			{
				// bus entries must have the same root name and go in order
				String lastnetname = null;
				for(j=0; j<total; j++)
				{
					CellSignal wl = outerSignalList[j];
					String thisnetname = getSignalName(wl);
					if (wl.isDescending())
					{
						if (!descending) break;
					} else
					{
						if (descending) break;
					}

					int openSquare = thisnetname.indexOf('[');
					if (openSquare < 0) break;
					if (j > 0)
					{
						int li = 0;
						for( ; li < lastnetname.length(); li++)
						{
							if (thisnetname.charAt(li) != lastnetname.charAt(li)) break;
							if (lastnetname.charAt(li) == '[') break;
						}
						if (lastnetname.charAt(li) != '[' || thisnetname.charAt(li) != '[') break;
						int thisIndex = TextUtils.atoi(thisnetname.substring(li+1));
						int lastIndex = TextUtils.atoi(lastnetname.substring(li+1));
						if (thisIndex != lastIndex + 1) break;
					}
					lastnetname = thisnetname;
				}
				if (j < total) breakBus = true;
			}
		}

		if (name != null) infstr.append("." + name + "(");
		if (breakBus)
		{
			infstr.append("{");
			int start = 0, end = total-1;
			int order = 1;
			if (descending)
			{
				start = total-1;
				end = 0;
				order = -1;
			}
			for(int j=start; ; j += order)
			{
				if (j != start)
					infstr.append(", ");
				CellSignal cs = outerSignalList[j];
				infstr.append(getSignalName(cs));
				if (j == end) break;
			}
			infstr.append("}");
		} else
		{
			CellSignal lastCs = outerSignalList[0];
			String lastNetName = getSignalName(lastCs);
			int openSquare = lastNetName.indexOf('[');
			CellSignal cs = outerSignalList[total-1];
			String netName = getSignalName(cs);
			int i = 0;
			for( ; i<netName.length(); i++)
			{
				if (netName.charAt(i) == '[') break;
				infstr.append(netName.charAt(i));
			}
			if (descending)
			{
				int first = TextUtils.atoi(netName.substring(i+1));
				int second = TextUtils.atoi(lastNetName.substring(openSquare+1));
				infstr.append("[" + first + ":" + second + "]");
			} else
			{
				int first = TextUtils.atoi(netName.substring(i+1));
				int second = TextUtils.atoi(lastNetName.substring(openSquare+1));
				infstr.append("[" + second + ":" + first + "]");
			}
		}
		if (name != null) infstr.append(")");
	}

	/**
	 * Method to add text from all nodes in cell "np"
	 * (which have "verilogkey" text on them)