verilog.java

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

						printWriter.println("    wire " + global.getName() + ";");
					}
				}
				printWriter.println("endmodule");
			}
		}

		// prepare arcs to store implicit inverters
		Map<ArcInst,Integer> implicitHeadInverters = new HashMap<ArcInst,Integer>();
		Map<ArcInst,Integer> implicitTailInverters = new HashMap<ArcInst,Integer>();
		int impInvCount = 0;
		for(Iterator<ArcInst> it = cell.getArcs(); it.hasNext(); )
		{
			ArcInst ai = it.next();
			for(int e=0; e<2; e++)
			{
				if (!ai.isNegated(e)) continue;
				PortInst pi = ai.getPortInst(e);
				NodeInst ni = pi.getNodeInst();
				if (ni.getProto() == Schematics.tech().bufferNode || ni.getProto() == Schematics.tech().andNode ||
					ni.getProto() == Schematics.tech().orNode || ni.getProto() == Schematics.tech().xorNode)
				{
					if (Simulation.getVerilogUseAssign()) continue;
					if (pi.getPortProto().getName().equals("y")) continue;
				}

				// must create implicit inverter here
				if (e == ArcInst.HEADEND) implicitHeadInverters.put(ai, new Integer(impInvCount)); else
					implicitTailInverters.put(ai, new Integer(impInvCount));
				if (ai.getProto() != Schematics.tech().bus_arc) impInvCount++; else
				{
					int wid = cni.getNetList().getBusWidth(ai);
					impInvCount += wid;
				}
			}
		}

		// gather networks in the cell
		Netlist netList = cni.getNetList();

        // add in any user-specified defines
        includeTypedCode(cell, VERILOG_EXTERNAL_CODE_KEY, "external code");

		// write the module header
		printWriter.println();
		StringBuffer sb = new StringBuffer();
		sb.append("module " + cni.getParameterizedName() + "(");
		boolean first = true;
		for(Iterator<CellAggregateSignal> it = cni.getCellAggregateSignals(); it.hasNext(); )
		{
			CellAggregateSignal cas = it.next();
			if (cas.getExport() == null) continue;
			if (cas.getLowIndex() <= cas.getHighIndex() && cas.getIndices() != null)
			{
				// fragmented bus: write individual signals
				int [] indices = cas.getIndices();
				for(int i=0; i<indices.length; i++)
				{
					int ind = i;
					if (cas.isDescending()) ind = indices.length - i - 1;
					if (!first) sb.append(",");
					sb.append(" \\" + cas.getName() + "[" + indices[ind] + "] ");
					first = false;
				}
			} else
			{
				// simple name, add to module header
				if (!first) sb.append(", ");
				sb.append(cas.getName());
				first = false;
			}
		}
		sb.append(");\n");
		writeWidthLimited(sb.toString());
		definedModules.put(cni.getParameterizedName(), "Cell "+cell.libDescribe());

        // add in any user-specified parameters
        includeTypedCode(cell, VERILOG_PARAMETER_KEY, "parameters");

		// look for "wire/trireg" overrides
		for(Iterator<ArcInst> it = cell.getArcs(); it.hasNext(); )
		{
			ArcInst ai = it.next();
			Variable var = ai.getVar(WIRE_TYPE_KEY);
			if (var == null) continue;
			String wireType = var.getObject().toString();
			int overrideValue = 0;
			if (wireType.equalsIgnoreCase("wire")) overrideValue = 1; else
				if (wireType.equalsIgnoreCase("trireg")) overrideValue = 2;
			int busWidth = netList.getBusWidth(ai);
			for(int i=0; i<busWidth; i++)
			{
				Network net = netList.getNetwork(ai, i);
				CellSignal cs = cni.getCellSignal(net);
				if (cs == null) continue;
				cs.getAggregateSignal().setFlags(overrideValue);
			}
		}

		// write description of formal parameters to module
		first = true;
		for(Iterator<CellAggregateSignal> it = cni.getCellAggregateSignals(); it.hasNext(); )
		{
			CellAggregateSignal cas = it.next();
			Export pp = cas.getExport();
			if (pp == null) continue;

			String portType = "input";
			if (pp.getCharacteristic() == PortCharacteristic.OUT)
				portType = "output";
			else if (pp.getCharacteristic() == PortCharacteristic.BIDIR)
				portType = "inout";

			sb = new StringBuffer();
			sb.append("  " + portType);
			if (cas.getLowIndex() > cas.getHighIndex())
			{
				sb.append(" " + cas.getName() + ";");
			} else
			{
				int [] indices = cas.getIndices();
				if (indices != null)
				{
					for(int i=0; i<indices.length; i++)
					{
						int ind = i;
						if (cas.isDescending()) ind = indices.length - i - 1;
						if (i != 0) sb.append(",");
						sb.append(" \\" + cas.getName() + "[" + indices[ind] + "] ");
					}
					sb.append(";");
				} else
				{
					int low = cas.getLowIndex(), high = cas.getHighIndex();
					if (cas.isDescending())
					{
						low = cas.getHighIndex();   high = cas.getLowIndex();
					}
					sb.append(" [" + low + ":" + high + "] " + cas.getName() + ";");
				}
			}
			if (cas.getFlags() != 0)
			{
				if (cas.getFlags() == 1) sb.append("  wire"); else
					sb.append("  trireg");
				sb.append(" " + cas.getName() + ";");
			}
			sb.append("\n");
			writeWidthLimited(sb.toString());
			first = false;
		}
		if (!first) printWriter.println();

		// if writing standard cell netlist, do not netlist contents of standard cells
		if (Simulation.getVerilogStopAtStandardCells())
		{
			if (SCLibraryGen.isStandardCell(cell)) {
				printWriter.println("endmodule   /* " + cni.getParameterizedName() + " */");
				return;
			}
		}

		// describe power and ground nets
		if (cni.getPowerNet() != null) printWriter.println("  supply1 vdd;");
		if (cni.getGroundNet() != null) printWriter.println("  supply0 gnd;");

		// determine whether to use "wire" or "trireg" for networks
		String wireType = "wire";
		if (Simulation.getVerilogUseTrireg()) wireType = "trireg";

		// write "wire/trireg" declarations for internal single-wide signals
		int localWires = 0;
		for(int wt=0; wt<2; wt++)
		{
			first = true;
			for(Iterator<CellAggregateSignal> it = cni.getCellAggregateSignals(); it.hasNext(); )
			{
				CellAggregateSignal cas = it.next();
				if (cas.getExport() != null) continue;
				if (cas.isSupply()) continue;
				if (cas.getLowIndex() <= cas.getHighIndex()) continue;
				if (cas.isGlobal()) continue;

				String impSigName = wireType;
				if (cas.getFlags() != 0)
				{
					if (cas.getFlags() == 1) impSigName = "wire"; else
						impSigName = "trireg";
				}
				if ((wt == 0) ^ !wireType.equals(impSigName))
				{
					if (first)
					{
						initDeclaration("  " + impSigName);
					}
					addDeclaration(cas.getName());
					localWires++;
					first = false;
				}
			}
			if (!first) termDeclaration();
		}

		// write "wire/trireg" declarations for internal busses
		for(Iterator<CellAggregateSignal> it = cni.getCellAggregateSignals(); it.hasNext(); )
		{
			CellAggregateSignal cas = it.next();
			if (cas.getExport() != null) continue;
			if (cas.isSupply()) continue;
			if (cas.getLowIndex() > cas.getHighIndex()) continue;
			if (cas.isGlobal()) continue;

			int [] indices = cas.getIndices();
			if (indices != null)
			{
				for(int i=0; i<indices.length; i++)
				{
					int ind = i;
					if (cas.isDescending()) ind = indices.length - i - 1;
					printWriter.println("  " + wireType + " \\" + cas.getName() + "[" + indices[ind] + "] ;");
				}
			} else
			{
				if (cas.isDescending())
				{
					printWriter.println("  " + wireType + " [" + cas.getHighIndex() + ":" + cas.getLowIndex() + "] " + cas.getName() + ";");
				} else
				{
					printWriter.println("  " + wireType + " [" + cas.getLowIndex() + ":" + cas.getHighIndex() + "] " + cas.getName() + ";");
				}
			}
			localWires++;
		}
		if (localWires != 0) printWriter.println();

		// add "wire" declarations for implicit inverters
		if (impInvCount > 0)
		{
			initDeclaration("  " + wireType);
			for(int i=0; i<impInvCount; i++)
			{
				String impsigname = IMPLICITINVERTERSIGNAME + i;
				addDeclaration(impsigname);
			}
			termDeclaration();
		}

		// add in any user-specified declarations and code
        if (!Simulation.getVerilogStopAtStandardCells()) {
            // STA does not like general verilog code (like and #delay out ina inb etc)
            first = includeTypedCode(cell, VERILOG_DECLARATION_KEY, "declarations");
		    first |= includeTypedCode(cell, VERILOG_CODE_KEY, "code");
		    if (!first)
			    printWriter.println("  /* automatically generated Verilog */");
        }

        // accumulate port connectivity information for port directional consistency check
		Map<Network,List<Export>> instancePortsOnNet = new HashMap<Network,List<Export>>();

		// look at every node in this cell
		for(Iterator<Nodable> nIt = netList.getNodables(); nIt.hasNext(); )
		{
			Nodable no = nIt.next();
			NodeProto niProto = no.getProto();

			// not interested in passive nodes (ports electrically connected)
			PrimitiveNode.Function nodeType = PrimitiveNode.Function.UNKNOWN;
			if (!no.isCellInstance())
			{
				NodeInst ni = (NodeInst)no;
				Iterator<PortInst> pIt = ni.getPortInsts();
				if (pIt.hasNext())
				{
					boolean allConnected = true;
					PortInst firstPi = pIt.next();
					Network firstNet = netList.getNetwork(firstPi);
					for( ; pIt.hasNext(); )
					{
						PortInst pi = pIt.next();
						Network thisNet = netList.getNetwork(pi);
						if (thisNet != firstNet) { allConnected = false;   break; }
					}
					if (allConnected) continue;
				}
				nodeType = ni.getFunction();

				// special case: verilog should ignore R L C etc.
				if (nodeType.isResistor() || // == PrimitiveNode.Function.RESIST ||
					nodeType.isCapacitor() ||  // == PrimitiveNode.Function.CAPAC || nodeType == PrimitiveNode.Function.ECAPAC ||
					nodeType == PrimitiveNode.Function.INDUCT ||
					nodeType == PrimitiveNode.Function.DIODE || nodeType == PrimitiveNode.Function.DIODEZ)
						continue;
			}

			// look for a Verilog template on the prototype
			if (no.isCellInstance())
			{
				// if writing standard cell netlist, do not write out cells that
				// do not contain standard cells
				if (Simulation.getVerilogStopAtStandardCells())
				{
					if (!standardCells.containsStandardCell((Cell)niProto) &&
						!SCLibraryGen.isStandardCell((Cell)niProto)) continue;
				}

				Variable varTemplate = ((Cell)niProto).getVar(VERILOG_TEMPLATE_KEY);
				if (varTemplate != null)
				{
					if (varTemplate.getObject() instanceof String []) {
						String [] lines = (String [])varTemplate.getObject();
						writeWidthLimited("  /* begin Verilog_template for "+no.getProto().describe(false)+"*/\n");
						for (int i=0; i<lines.length; i++) {
							writeTemplate(lines[i], no, cni, context);
						}
						writeWidthLimited("  // end Verilog_template\n");
					} else {
						// special case: do not write out string "//"
						if (!((String)varTemplate.getObject()).equals("//")) {
							writeWidthLimited("  /* begin Verilog_template for "+no.getProto().describe(false)+"*/\n");
							writeTemplate((String)varTemplate.getObject(), no, cni, context);
							writeWidthLimited("  // end Verilog_template\n");
						}
					}
					continue;
				}
			}

            // look for a Verilog defparam template on the prototype
            // Defparam templates provide a mechanism for prepending per instance
            // parameters on verilog declarations
            if (no.isCellInstance())
            {
                Variable varDefparamTemplate = ((Cell)niProto).getVar(VERILOG_DEFPARAM_KEY);
                if (varDefparamTemplate != null)
                {
                    if (varDefparamTemplate.getObject() instanceof String []) {
                        String [] lines = (String [])varDefparamTemplate.getObject();
                        // writeWidthLimited("  /* begin Verilog_defparam for "+no.getProto().describe(false)+" */\n");
                        boolean firstDefparam = true;
                        for (int i=0; i<lines.length; i++) {
                        	//StringBuffer infstr = new StringBuffer();
                        	String defparam = new String();
                        	defparam = writeDefparam(lines[i], no, context);
                        	if (defparam.length() != 0)
                        	{
                        		if (firstDefparam)
                        		{
                        			writeWidthLimited("  /* begin Verilog_defparam for "+no.getProto().describe(false)+" */\n");
                        			firstDefparam = false;
                        		}
                        		writeWidthLimited(defparam);
                        	}
                        }
                        if (!firstDefparam)
                        {
                        	writeWidthLimited("  // end Verilog_defparam\n");
                        }
                    } else
                    {
                        // special case: do not write out string "//"
                        if (!((String)varDefparamTemplate.getObject()).equals("//"))
                        {
                        	String defparam = new String();
                        	defparam = writeDefparam((String)varDefparamTemplate.getObject(), no, context);
                        	if (defparam.length() != 0)
                        	{
                            	writeWidthLimited("  /* begin Verilog_defparam for "+no.getProto().describe(false)+"*/\n");
                        		writeWidthLimited(defparam);
                                writeWidthLimited("  // end Verilog_defparam\n");
                        	}

                        }
                    }
                }
            }