verilog.java

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

/* -*- tab-width: 4 -*-
 *
 * Electric(tm) VLSI Design System
 *
 * File: Verilog.java
 * Input/output tool: Verilog Netlist output
 * Written by Steven M. Rubin, Sun Microsystems.
 *
 * Copyright (c) 2003 Sun Microsystems and Static Free Software
 *
 * Electric(tm) is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 3 of the License, or
 * (at your option) any later version.
 *
 * Electric(tm) is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with Electric(tm); see the file COPYING.  If not, write to
 * the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
 * Boston, Mass 02111-1307, USA.
 */
package com.sun.electric.tool.io.output;

import com.sun.electric.database.hierarchy.Cell;
import com.sun.electric.database.hierarchy.Export;
import com.sun.electric.database.hierarchy.HierarchyEnumerator;
import com.sun.electric.database.hierarchy.Library;
import com.sun.electric.database.hierarchy.Nodable;
import com.sun.electric.database.hierarchy.View;
import com.sun.electric.database.network.Global;
import com.sun.electric.database.network.Netlist;
import com.sun.electric.database.network.Network;
import com.sun.electric.database.prototype.NodeProto;
import com.sun.electric.database.prototype.PortCharacteristic;
import com.sun.electric.database.prototype.PortProto;
import com.sun.electric.database.text.TextUtils;
import com.sun.electric.database.text.Version;
import com.sun.electric.database.topology.ArcInst;
import com.sun.electric.database.topology.Connection;
import com.sun.electric.database.topology.NodeInst;
import com.sun.electric.database.topology.PortInst;
import com.sun.electric.database.variable.CodeExpression;
import com.sun.electric.database.variable.VarContext;
import com.sun.electric.database.variable.Variable;
import com.sun.electric.technology.PrimitiveNode;
import com.sun.electric.technology.technologies.Generic;
import com.sun.electric.technology.technologies.Schematics;
import com.sun.electric.tool.generator.sclibrary.SCLibraryGen;
import com.sun.electric.tool.io.input.verilog.VerilogData;
import com.sun.electric.tool.io.input.verilog.VerilogReader;
import com.sun.electric.tool.simulation.Simulation;
import com.sun.electric.tool.user.User;
import com.sun.electric.tool.user.dialogs.BusParameters;

import java.util.ArrayList;
import java.util.Collection;
import java.util.Date;
import java.util.HashMap;
import java.util.HashSet;
import java.util.Iterator;
import java.util.List;
import java.util.Map;
import java.util.Set;

/**
 * This is the Simulation Interface tool.
 */
public class Verilog extends Topology
{
	/** A set of keywords that are reserved in Verilog */
	private static Set<String> reservedWords;
	static
	{
		reservedWords = new HashSet<String>();
		reservedWords.add("always");
		reservedWords.add("and");
		reservedWords.add("assign");
		reservedWords.add("attribute");
		reservedWords.add("begin");
		reservedWords.add("buf");
		reservedWords.add("bufif0");
		reservedWords.add("bufif1");
		reservedWords.add("case");
		reservedWords.add("casex");
		reservedWords.add("casez");
		reservedWords.add("cmos");
		reservedWords.add("deassign");
		reservedWords.add("default");
		reservedWords.add("defpram");
		reservedWords.add("disable");
		reservedWords.add("edge");
		reservedWords.add("else");
		reservedWords.add("end");
		reservedWords.add("endattribute");
		reservedWords.add("endcase");
		reservedWords.add("endfunction");
		reservedWords.add("endmodule");
		reservedWords.add("endprimitive");
		reservedWords.add("endspecify");
		reservedWords.add("endtable");
		reservedWords.add("endtask");
		reservedWords.add("event");
		reservedWords.add("for");
		reservedWords.add("force");
		reservedWords.add("forever");
		reservedWords.add("fork");
		reservedWords.add("function");
		reservedWords.add("highz0");
		reservedWords.add("highz1");
		reservedWords.add("if");
		reservedWords.add("initial");
		reservedWords.add("inout");
		reservedWords.add("input");
		reservedWords.add("integer");
		reservedWords.add("join");
		reservedWords.add("large");
		reservedWords.add("macromodule");
		reservedWords.add("meduim");
		reservedWords.add("module");
		reservedWords.add("nand");
		reservedWords.add("negedge");
		reservedWords.add("nmos");
		reservedWords.add("nor");
		reservedWords.add("not");
		reservedWords.add("notif0");
		reservedWords.add("notif1");
		reservedWords.add("or");
		reservedWords.add("output");
		reservedWords.add("parameter");
		reservedWords.add("pmos");
		reservedWords.add("posedge");
		reservedWords.add("primitive");
		reservedWords.add("pull0");
		reservedWords.add("pull1");
		reservedWords.add("pulldown");
		reservedWords.add("pullup");
		reservedWords.add("rcmos");
		reservedWords.add("real");
		reservedWords.add("realtime");
		reservedWords.add("reg");
		reservedWords.add("release");
		reservedWords.add("repeat");
		reservedWords.add("rtranif1");
		reservedWords.add("scalared");
		reservedWords.add("signed");
		reservedWords.add("small");
		reservedWords.add("specify");
		reservedWords.add("specpram");
		reservedWords.add("strength");
		reservedWords.add("strong0");
		reservedWords.add("strong1");
		reservedWords.add("supply0");
		reservedWords.add("supply1");
		reservedWords.add("table");
		reservedWords.add("task");
		reservedWords.add("time");
		reservedWords.add("tran");
		reservedWords.add("tranif0");
		reservedWords.add("tranif1");
		reservedWords.add("tri");
		reservedWords.add("tri0");
		reservedWords.add("tri1");
		reservedWords.add("triand");
		reservedWords.add("trior");
		reservedWords.add("trireg");
		reservedWords.add("unsigned");
		reservedWords.add("vectored");
		reservedWords.add("wait");
		reservedWords.add("wand");
		reservedWords.add("weak0");
		reservedWords.add("weak1");
		reservedWords.add("while");
		reservedWords.add("wire");
		reservedWords.add("wor");
		reservedWords.add("xnor");
		reservedWords.add("xor");
	}

	/** maximum size of output line */						private static final int MAXDECLARATIONWIDTH = 80;
	/** name of inverters generated from negated wires */	private static final String IMPLICITINVERTERNODENAME = "Imp";
	/** name of signals generated from negated wires */		private static final String IMPLICITINVERTERSIGNAME = "ImpInv";

	/** key of Variable holding verilog code. */			public static final Variable.Key VERILOG_CODE_KEY = Variable.newKey("VERILOG_code");
	/** key of Variable holding verilog declarations. */	public static final Variable.Key VERILOG_DECLARATION_KEY = Variable.newKey("VERILOG_declaration");
    /** key of Variable holding verilog parameters. */		public static final Variable.Key VERILOG_PARAMETER_KEY = Variable.newKey("VERILOG_parameter");
    /** key of Variable holding verilog code that is 
     ** external to the module. */							public static final Variable.Key VERILOG_EXTERNAL_CODE_KEY = Variable.newKey("VERILOG_external_code");
	/** key of Variable holding verilog wire time. */		public static final Variable.Key WIRE_TYPE_KEY = Variable.newKey("SIM_verilog_wire_type");
	/** key of Variable holding verilog templates. */		public static final Variable.Key VERILOG_TEMPLATE_KEY = Variable.newKey("ATTR_verilog_template");
    /** key of Variable holding verilog defparams. */		public static final Variable.Key VERILOG_DEFPARAM_KEY = Variable.newKey("ATTR_verilog_defparam");
	/** key of Variable holding file name with Verilog. */	public static final Variable.Key VERILOG_BEHAVE_FILE_KEY = Variable.newKey("SIM_verilog_behave_file");
	/** those cells that have overridden models */			private Set<Cell> modelOverrides = new HashSet<Cell>();
	/** those cells that have modules defined */			private Map<String,String> definedModules = new HashMap<String,String>(); // key: module name, value: source description
	/** those cells that have primitives defined */			private Map<Cell,VerilogData.VerilogModule> definedPrimitives = new HashMap<Cell,VerilogData.VerilogModule>(); // key: module name, value: VerilogModule
	/** map of cells that are or contain standard cells */  private SCLibraryGen.StandardCellHierarchy standardCells = new SCLibraryGen.StandardCellHierarchy();
    /** file we are writing to */                           private String filePath;

    public static String getVerilogSafeName(String name, boolean isNode, boolean isBus) {
    	Verilog v = new Verilog();
    	if (isNode) return v.getSafeCellName(name);
    	return v.getSafeNetName(name, isBus);
    }

	/**
	 * The main entry point for Verilog deck writing.
	 * @param cell the top-level cell to write.
	 * @param context the hierarchical context to the cell.
	 * @param filePath the disk file to create.
	 */
	public static void writeVerilogFile(Cell cell, VarContext context, String filePath)
	{
		Verilog out = new Verilog();
        if (out.openTextOutputStream(filePath)) return;
        out.filePath = filePath;
		if (out.writeCell(cell, context)) return;
		if (out.closeTextOutputStream()) return;
		System.out.println(filePath + " written");
	}

	/**
	 * Creates a new instance of Verilog
	 */
	Verilog()
	{
	}

	protected void start()
	{
		// parameters to the output-line-length limit and how to break long lines
		setOutputWidth(MAXDECLARATIONWIDTH, false);
		setContinuationString("      ");

		// write header information
		printWriter.println("/* Verilog for " + topCell + " from " + topCell.getLibrary() + " */");
		emitCopyright("/* ", " */");
		if (User.isIncludeDateAndVersionInOutput())
		{
			printWriter.println("/* Created on " + TextUtils.formatDate(topCell.getCreationDate()) + " */");
			printWriter.println("/* Last revised on " + TextUtils.formatDate(topCell.getRevisionDate()) + " */");
			printWriter.println("/* Written on " + TextUtils.formatDate(new Date()) +
				" by Electric VLSI Design System, version " + Version.getVersion() + " */");
		} else
		{
			printWriter.println("/* Written by Electric VLSI Design System */");
		}

		if (Simulation.getVerilogStopAtStandardCells()) {
			// enumerate to find which cells contain standard cells
			HierarchyEnumerator.enumerateCell(topCell, VarContext.globalContext, standardCells);
			for (Cell acell : standardCells.getDoesNotContainStandardCellsInHier()) {
				System.out.println("Warning: Not netlisting cell "+acell.describe(false)+" because it does not contain any standard cells.");
			}
			if (standardCells.getNameConflict()) {
				System.out.println("Name conflicts found, please see above messages");
			}
		}
	}

	protected void done()
	{
    	// Remove this call that auto-overrides the new user visible preference
		// Simulation.setVerilogStopAtStandardCells(false);
	}

	protected boolean skipCellAndSubcells(Cell cell) {

        // do not netlist contents of standard cells
        // also, if writing a standard cell netlist, ignore all verilog views, verilog templates, etc.
        if (Simulation.getVerilogStopAtStandardCells()) {
            if (!standardCells.containsStandardCell(cell)) {
                return true;
            } else {
                return false;
            }
        }

		// do not write modules for cells with verilog_templates defined
		// also skip their subcells
		if (cell.getVar(VERILOG_TEMPLATE_KEY) != null) {
			return true;
		}
		// also skip subcells if a behavioral file specified.
		// If one specified, write it out here and skip both cell and subcells
		if (CellModelPrefs.verilogModelPrefs.isUseModelFromFile(cell)) {
			String fileName = CellModelPrefs.verilogModelPrefs.getModelFile(cell);
            if (filePath.equals(fileName)) {
                System.out.println("Error: Use Model From File file path for cell "+cell.describe(false)+" is the same as the file being written, skipping.");
                return false;
            }
            // check that data from file is consistent
			VerilogReader reader = new VerilogReader();
			VerilogData data = reader.parseVerilog(fileName, true);
			if (data == null) {
				System.out.println("Error reading include file: "+fileName);
				return false;
			}
			if (!checkIncludedData(data, cell, fileName))
				return false;

			if (!modelOverrides.contains(cell))
			{
				printWriter.println("`include \"" + fileName + "\"");
				modelOverrides.add(cell);
			}
			return true;
		}

		// use library behavior if it is available
		Cell verViewCell = cell.otherView(View.VERILOG);
		if (verViewCell != null)
		{
			String [] stringArray = verViewCell.getTextViewContents();
			if (stringArray != null)
			{
				if (stringArray.length > 0) {
					String line = stringArray[0].toLowerCase();
					if (line.startsWith("do not use")) {
						return false;
					}
				}
				VerilogReader reader = new VerilogReader();
				VerilogData data = reader.parseVerilog(stringArray, cell.getLibrary().getName());
				if (data == null) {
					System.out.println("Error parsing Verilog View for cell "+cell.describe(false));
					return false;
				}
				if (!checkIncludedData(data, cell, null))
					return false;

				// write to output file
				System.out.println("Info: Netlisting Verilog view of "+cell.describe(false));
				printWriter.println();
				printWriter.println("/* Verilog view of "+verViewCell.libDescribe()+" */");
				for(int i=0; i<stringArray.length; i++)
					printWriter.println(stringArray[i]);
			}
			return true;
		}

		return false;
	}

	/**
	 * Method to write cellGeom
	 */
	protected void writeCellTopology(Cell cell, CellNetInfo cni, VarContext context, Topology.MyCellInfo info)
	{
		if (cell == topCell) {
			// gather all global signal names
			Netlist netList = cni.getNetList();
			Global.Set globals = netList.getGlobals();
			int globalSize = globals.size();

			// see if any globals besides power and ground to write
			List<Global> globalsToWrite = new ArrayList<Global>();
			for (int i=0; i<globalSize; i++) {
				Global global = globals.get(i);
				if (global == Global.power || global == Global.ground) continue;
				globalsToWrite.add(global);
			}

			if (globalsToWrite.size() > 0)
			{
				printWriter.println("\nmodule glbl();");
				for(int i=0; i<globalsToWrite.size(); i++)
				{
					Global global = globalsToWrite.get(i);
					if (Simulation.getVerilogUseTrireg())
					{
						printWriter.println("    trireg " + global.getName() + ";");
					} else
					{