verilogreader.java

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

        return verilogData;
    }

    public Cell createCellsOnly(VerilogData verilogData, Job job)
    {
        Cell theCell = null;

        Library library = Library.newInstance(verilogData.name, null);
        String topCellName = TextUtils.getFileNameWithoutExtension(verilogData.name);
        buildCells(verilogData, library, false);
        theCell = library.findNodeProto(topCellName);
        if (job != null)
            System.out.println("Accumulative time after creating cells '" + verilogData.name + "' " + job.getInfo());
        return theCell; // still work because VerilogReader remembers the top cell
    }

    public VerilogData readVerilogOnly(String file, boolean fullOyster, Job job)
    {
        URL fileURL = TextUtils.makeURLToFile(file);
        VerilogData verilogData = parseVerilog(file, fullOyster);

        if (verilogData == null) return null; // error

        if (job != null)
            System.out.println("Accumulative time before creating cells '" + file + "' " + job.getInfo());
        return verilogData;
    }

    public Cell readVerilog(String testName, String file, boolean createCells, boolean fullOyster, Job job)
    {
        URL fileURL = TextUtils.makeURLToFile(file);
        VerilogData verilogData = parseVerilog(file, fullOyster);
        if (verilogData == null) return null; // error
        int index = file.lastIndexOf("/");
        String libName = file.substring(index+1);

        if (job != null)
            System.out.println("Accumulative time before creating cells '" + testName + "' " + job.getInfo());
        // Last verilogName must be the top one
        if (createCells)
        {
            Library library = Library.newInstance(libName, null);
            String topCellName = TextUtils.getFileNameWithoutExtension(fileURL);
            topCell = buildCells(verilogData, library, fullOyster);
            Cell c = library.findNodeProto(topCellName);
            if (c == null)
            {
                System.out.println("Check this case in readVerilog");  // is it relevant?
//                assert(false);
            }
            else
                topCell = c;
        }
        if (job != null)
            System.out.println("Accumulative time after creating cells '" + testName + "' " + job.getInfo());
        return topCell; // still work because VerilogReader remembers the top cell
    }

    private VerilogData parseVerilogInternal(String fileName, boolean simplifyWires)
    {
        VerilogData verilogData = new VerilogData(fileName);

        try
        {
            String nextToken = null;
            String key = null;

            for(;;)
            {
                if (nextToken != null) // get last token read by network section
                {
                    key = nextToken;
                    nextToken = null;
                }
                else
                    key = getAKeyword();

                if (key == null) break; // end of the file

                if (key.startsWith("/"))
                {
                    getRestOfLine();
                    continue; // comments
                }
                if (key.equals("module") || key.equals("primitive"))
                {
                    boolean primitive = key.equals("primitive");
                    nextToken = readCell(verilogData, primitive);
                }
            }
        } catch (IOException e)
        {
            System.out.println("ERROR reading Verilog file");
        }

        // Simplify wires?: a[1], a[2], a[3] -> a[1:3]
        if (simplifyWires) verilogData.simplifyWires();
        return verilogData;
    }

    /**************************************************************************************************************
     * Functions to build Electric cells from VerilogData. Functions are here to simplify the VerilogData class
     * and dependent classes
     *************************************************************************************************************/

    /**
     * Function to build cells from a VerilogData object
     * @param verilogCell
     * @param lib
     * @param fullOyster
     */
    private Cell buildCells(VerilogData verilogCell, Library lib, boolean fullOyster)
    {
        Cell topCell = null; // assumes the first module in the list is the top cell

        for (VerilogData.VerilogModule module : verilogCell.getModules())
        {
            Cell cell = buildCellFromModule(module, lib, fullOyster);
            if (topCell == null)
                topCell = cell;
        }
        return topCell;
    }

    private void addPins(VerilogData.VerilogConnection port, Cell cell, boolean addExport, boolean fullOyster)
    {
        String name = port.name;
        PortCharacteristic portType = port.getPortType();

        List<String> pinNames = port.getPinNames(fullOyster); // This function controls if busses are split into multi pins
        // or as just one element

        Collections.sort(pinNames);
        for (String pinName : pinNames)
        {
            PrimitiveNode primitive = Schematics.tech().wirePinNode;
            NodeInst ni = cell.findNode(pinName);

            if (ni == null)
            {
                ni = NodeInst.newInstance(primitive, getNextLocation(cell),
                        primitiveWidth, primitiveHeight,
    //                        primitive.getDefWidth(), primitive.getDefHeight(),
                        cell, Orientation.IDENT, pinName, 0);
                if (addExport)
                {
                    Export ex = Export.newInstance(cell, ni.getOnlyPortInst(), pinName, portType);
                }
            }
            else
            {
                assert(false);
                 System.out.println("Wire/Input/Output " + pinName + " exists");
            }
        }
//            PrimitiveNode primitive = (port.busPins==null) ? Schematics.tech.wirePinNode :
//                    Schematics.tech.busPinNode;
//            NodeInst ni = NodeInst.newInstance(primitive, getNextLocation(cell),
//                    primitiveWidth, primitiveHeight,
////                        primitive.getDefWidth(), primitive.getDefHeight(),
//                    cell, Orientation.IDENT, name, 0);
//            Export ex = Export.newInstance(cell, ni.getOnlyPortInst(), name);
//            ex.setCharacteristic(portType);
    }

    /**
     * Function to build cell fro a VerilogModule object
     * @param lib
     * @param fullOyster
     * @return Cell object representing this module
     */
    private Cell buildCellFromModule(VerilogData.VerilogModule module, Library lib, boolean fullOyster)
    {
        String cellName = module.name + View.SCHEMATIC.getAbbreviationExtension();
        Cell cell = lib.findNodeProto(cellName);
        if (cell != null) return cell; // already created;

        cell = Cell.makeInstance(lib, cellName);
        cell.setTechnology(Schematics.tech());
        // Adding essential bounds for now
        // Change Sept 08, 07 Out
//        NodeInst.makeInstance(essentialBounds, new Point2D.Double(10,10), 1, 1, cell,
//                Orientation.IDENT, null, 0);
//        NodeInst.makeInstance(essentialBounds, new Point2D.Double(-10,-10), 1, 1, cell,
//                Orientation.RR, null, 0);

        List<Object> all = module.getAllSorted();
        for (Object obj : all)
        {

            if (obj instanceof VerilogData.VerilogWire)
        // wires first to determine which pins are busses or simple pins
//        for (VerilogData.VerilogWire wire : module.getWires())
        {
            VerilogData.VerilogWire wire = (VerilogData.VerilogWire)obj;
            addPins(wire, cell, false, fullOyster);
        }

        else if (obj instanceof VerilogData.VerilogPort)
        // inputs/outputs/inouts/supplies
//        for (VerilogData.VerilogPort port : module.getPorts())
        {
            //Point2D center, double width, double height, Cell parent)
            VerilogData.VerilogPort port = (VerilogData.VerilogPort)obj;
            String name = port.name;
            PortCharacteristic portType = port.type;

            // input/output/inout
            if (portType == PortCharacteristic.BIDIR ||
                    portType == PortCharacteristic.IN ||
                    portType == PortCharacteristic.OUT ||
                    portType == PortCharacteristic.CLK ||
                    portType == PortCharacteristic.UNKNOWN) // unknown when modules are read as instances
            {
                // new code
                addPins(port, cell, true, fullOyster);
            }
            else if (portType == PortCharacteristic.PWR ||
                    portType == PortCharacteristic.GND)
            {
                boolean power = portType == PortCharacteristic.PWR;
                PrimitiveNode np = (power) ? Schematics.tech().powerNode : Schematics.tech().groundNode;
                Point2D.Double p = getNextLocation(cell);
                double height = primitiveHeight; //np.getDefHeight();
                NodeInst supply = NodeInst.newInstance(np, p,
                        primitiveWidth, height,
                        cell, Orientation.IDENT, name, 0);
                // extra pin
                NodeInst ni = NodeInst.newInstance(Schematics.tech().wirePinNode, new Point2D.Double(p.getX(), p.getY()+height/2),
                        0.5, 0.5,
        //                Schematics.tech.wirePinNode.getDefWidth(), Schematics.tech.wirePinNode.getDefHeight(),
                        cell, Orientation.IDENT, name+"@0", 0);

                ArcInst.makeInstanceBase(Schematics.tech().wire_arc, 0.0,
//                ArcInst.makeInstanceFull(Schematics.tech.wire_arc, 0.0 /*Schematics.tech.wire_arc.getDefaultLambdaFullWidth()*/,
                    ni.getOnlyPortInst(), supply.getOnlyPortInst(), null, null, name);

                Export ex = Export.newInstance(cell, ni.getOnlyPortInst(), name, portType);
            }
            else
                System.out.println("Skipping this characteristic?");
//                    assert(false); // it should not reach this point.
        }
        }

        // instances
        for (VerilogData.VerilogInstance inst : module.getInstances())
        {
            buildNodeInstFromModule(inst, lib, cell, fullOyster);
        }

        // making icon
        if (fullOyster)
            ViewChanges.makeIconViewNoGUI(cell, true, true);

        return cell; // not too much sense?
    }

    /**
     * Function to build a NodeInst object from a VerilogInstance object
     * @param inst
     * @param lib
     * @param parent
     * @param fullOyster
     */
    Cell buildNodeInstFromModule(VerilogData.VerilogInstance inst, Library lib, Cell parent, boolean fullOyster)
    {
        Cell schematics = buildCellFromModule(inst.element, lib, fullOyster);
        Cell icon = (fullOyster) ? schematics.iconView() : schematics;
//        if (icon == null)
//        assert(icon != null);

        // Only for benchmarks schematics in
        NodeInst cellInst = NodeInst.newInstance(icon, getNextLocation(parent), 10, 10, parent,
                Orientation.IDENT, inst.name, 0);

        for (VerilogData.VerilogPortInst port : inst.ports)
        {
            List<String> localPorts = port.getPortNames();

            // Start and end are only valid for bus wires/inputs. The pin numbers should be in the order
            // they were defined in the port (ascendent or descendent)
            int startPort = port.port.start;
            int endPort = port.port.end;
            int count = startPort;
            boolean asc = (startPort < endPort);

            for (String s : localPorts)
            {
                NodeInst pin = parent.findNode(s);  // not sure if this should be done per cell or ask

                if (pin == null)
                {
                        int index = s.indexOf("[");
                        if (index != -1)
                        {
                            s = s.substring(0, index);
                            pin = parent.findNode(s);
                        }
                }
                if (pin == null)
                {
                    // Still missing vss code?
                     if (Job.getDebug())
                            System.out.println("Unknown signal " + s + " in cell " + parent.describe(false));
                        PrimitiveNode primitive = (port.port.isBusConnection()) ? Schematics.tech().busPinNode : Schematics.tech().wirePinNode;
                        pin = NodeInst.newInstance(primitive, getNextLocation(parent),
                                primitiveWidth, primitiveHeight,
                                parent, Orientation.IDENT, /*null*/s, 0);  // not sure why it has to be null?
                }

                ArcProto node = (pin.getProto() == Schematics.tech().busPinNode) ? Schematics.tech().bus_arc : Schematics.tech().wire_arc;
                String exportName = port.port.name;
                if (port.port.isBusConnection())
                {
                    // add bit so the pin can be found.
                    exportName += "[" + count + "]";
                }
                PortInst ex = cellInst.findPortInst(exportName);
                assert(ex != null); // it can't work without export. Check this case if fails
                ArcInst ai = ArcInst.makeInstanceBase(node, 0.0,
//                ArcInst ai = ArcInst.makeInstanceFull(node, 0.0 /*node.getDefaultLambdaFullWidth()*/,
                        pin.getOnlyPortInst(), ex, null, null, s);
                if (ai == null)
                    assert(ai != null);
                ai.setFixedAngle(false);
                if (asc) count++;
                else count--;
            }
        }
        return schematics;
    }
}