verilogreader.java

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

                key = "end";
            if (input.contains(key))
                return; // finish
        }
    }

    private String readInputOutput(VerilogData.VerilogModule module,
                                   PortCharacteristic portType) throws IOException
    {
        for (;;)
        {
            String input = getRestOfLine();
            StringTokenizer parse = new StringTokenizer(input, ";,", true); // extracting only input name

            while (parse.hasMoreTokens())
            {
                String net = parse.nextToken();
                if (net.equals(","))
                    continue;
                if (net.equals(";"))
                {
                    return null; // done
                }
                StringTokenizer p = new StringTokenizer(net, " \t", false); // extracting only input name
                List<String> l = new ArrayList<String>(2);
                while (p.hasMoreTokens())
                {
                    String name = p.nextToken();
                    l.add(name); // it could be "input a;" or "input [9:0] a;"
                }
                PrimitiveNode primitive = Schematics.tech().wirePinNode;
                int size = l.size();
                if (size == 0) continue;
                assert(size == 1 || size == 2);
                String name = l.get(size - 1);
                if (l.size() == 2) // "input a[];"
                {
//                    name += l.get(0); busPin not longer containing [x:y]
                    primitive = Schematics.tech().busPinNode;
                }

                VerilogData.VerilogPort export = module.findPort(name);
                // input a, b, c
                // ,d, c got problems to parse
                if (Job.getDebug())
                    assert(export != null);
                if (export != null)
                {
                    // except for clk!!
                    if (export.type != PortCharacteristic.UNKNOWN && export.type != portType)
                        System.out.println("Inconsistency in asigning port type in " + name + ". Found " + portType +
                        " and was " + export.type);
    //                    else
                        export.type = portType;
                    if (l.size() == 2)
                        export.setBusInformation(l.get(0));
                }
            }
        }
        // never reach this point
    }

    private String readCell(VerilogData verilogData, boolean primitive) throws IOException
    {
        List<String> inputs = new ArrayList<String>(10);
        readCellHeader(inputs);

        String cellName = inputs.get(0);
        VerilogData.VerilogModule module = null;
        Cell cell = null;

        module = verilogData.getModule(cellName);
        if (module == null)
            module = verilogData.addModule(cellName, primitive);
        module.setValid(true);
        // adding ports in modules: from 1 -> inputs.size()-1;
        for (int i = 1; i < inputs.size(); i++)
            module.addPort(inputs.get(i), true);

        String nextToken = null;

        for (;;)
        {
            String key = null;
            if (nextToken != null) // get last token read by network section
            {
                key = nextToken;
                nextToken = null;
            }
            else
                key = getAKeyword();

            if (key.startsWith("/")) // comment
            {
                getRestOfLine();
                continue;
            }

            if (key.startsWith("endmodule") || key.startsWith("endprimitive"))
            {
                // done with this cell
                return null;
            }

            if (key.equals("wire"))
            {
                readWiresAndSupplies(module, true, false);
                continue;
            }
            if (key.startsWith("tri"))
                assert(false); // not implemented

            if (key.equals("input"))
            {
                readInputOutput(module, PortCharacteristic.IN);
                continue;
            }
            if (key.equals("output"))
            {
                readInputOutput(module, PortCharacteristic.OUT);
                continue;
            }
            if (key.equals("inout"))
            {
                readInputOutput(module, PortCharacteristic.BIDIR);
                continue;
            }

            if (key.startsWith("supply"))
            {
                boolean power = key.contains("supply1");
                readWiresAndSupplies(module, false, power);
                continue;
            }

            // ignoring some elements
            if (key.equals("assign") || key.startsWith("always") || key.startsWith("initial")
                    || key.startsWith("reg") || key.startsWith("table") || key.startsWith("specify"))
            {
                if (Job.getDebug())
                    System.out.println("Ignoring " + key);
                String endStatement = null;
                if (key.startsWith("table"))
                    endStatement = "endtable";
                else if (key.startsWith("specify"))
                    endStatement = "endspecify";
                ignoreUntilEndOfStatement(endStatement); // either ; or end
                continue;
            }

//            if (verilogData == null)
            {
                if (key.equals("tranif1")) // transistors
                {
                    // reading gates
                    //tranif1 nmos4p_0(gnd, gnd, vPlt); -> nmos
                    assert(false); // implement again
                    nextToken = readGate(cell, PrimitiveNode.Function.TRANMOS);
                    continue;
                }
                if (key.equals("tranif0")) // transistors
                {
                    // reading gates
                    //tranif1 nmos4p_0(gnd, gnd, vPlt); -> nmos
                    assert(false); // implement again
                    nextToken = readGate(cell, PrimitiveNode.Function.TRAPMOS);
                    continue;
                }
            }

            // reading cell instances
            VerilogData.VerilogModule element = verilogData.getModule(key);

            if (element == null) // it hasn't been created
            {
                element = verilogData.addModule(key, false); // assuming latches and other elements are treat as subcells
            }

            CellInstance info = readInstance(module, element);
        }
        // not reaching this point.
    }

    /**
     * Method to get next X,Y position of the NodeInst in matrix. It also increments the counter for the next elements.
     * @return Point2D.Double represeting the NodeInst location
     */
    private Point2D.Double getNextLocation(Cell cell)
    {
        Point2D.Double point = locationMap.get(cell);
        double xPos = 0, yPos = 0;

        if (point != null) // first time
        {
            xPos = point.getX();
            yPos = point.getY();
        }
        double x = xPos*nodeWidth, y = yPos*nodeWidth;
        Point2D.Double p = new Point2D.Double(x, y);
        if (x > maxWidth)
        {
            yPos++; xPos = 0;
        }
        else
            xPos++;
        point = new Point2D.Double(xPos, yPos);
        locationMap.put(cell, point); // storing data for next node in cell
        return p;
    }

    /**
     * Method to read gate information including ports
     * @param cell
     * @param function
     * @return Next string to evaluate
     */
    private String readGate(Cell cell, PrimitiveNode.Function function) throws IOException
    {
        String input = getRestOfLine();
        StringTokenizer parse = new StringTokenizer(input, "(;, \t)", false); // extracting only input name
        List<String> list = new ArrayList<String>(2);

        while (parse.hasMoreTokens())
        {
            String value = parse.nextToken();
            list.add(value) ;
        }
        Orientation orient = Orientation.fromAngle(900);
//        String gateName = list.get(0);
        double width = Schematics.tech().transistorNode.getDefWidth();
        double height = Schematics.tech().transistorNode.getDefHeight();
        Point2D p = getNextLocation(cell);
        NodeInst ni = NodeInst.newInstance(Schematics.tech().transistorNode, p, width, height,
                                       cell, orient, null /*gateName*/, 0);
        Schematics.tech().transistorNode.getTechnology().setPrimitiveFunction(ni, function);
        transistors.add(ni);
        PortInst[] ports = new PortInst[3];
        int count = 0;

        for (Iterator<PortInst> it = ni.getPortInsts(); it.hasNext();)
        {
            ports[count++] = it.next();
        }

        for (int i = 1; i < list.size(); i++)
        {
            // Gate is the first port, then source and the last one is drain
            String name = list.get(i);
//            NodeInst pin = cell.findNode(name);
            // if pin already exists, the name will be composed
//            String pinName = (pin!=null) ? gateName+"-"+name : name;
//            parse = new StringTokenizer(name, "[", false); // extracting possible bus name
//            String realName = parse.nextToken();
//            NodeInst pin = cell.findNode(realName);
//            boolean wirePin = (name.equals(realName));
//            assert(pin != null);
            int pos = (3 + i) % 3; // the first port in g in Electric primitive which is the last (control) port in Verilog
            double posX = p.getX(), posY = p.getY();
            switch (pos)
            {
                case 0: // gnd
                    posX -= width/2;
                    break;
                case 1: // source
                    posX += width/2; posY -= height/2;
                    break;
                case 2: // drain
                    posX += width/2; posY += height/2;
                    break;
            }
//            PrimitiveNode primitive = (wirePin) ? Schematics.tech.wirePinNode : Schematics.tech.busPinNode;
            PrimitiveNode primitive = Schematics.tech().wirePinNode;
            ni = NodeInst.newInstance(primitive, new Point2D.Double(posX, posY),
                        primitiveWidth /*primitive.getDefWidth()*/, primitiveHeight /*primitive.getDefHeight()*/,
                        cell, Orientation.IDENT, null /*pinName*/, 0);

            ArcInst.makeInstanceBase(Schematics.tech().wire_arc, 0.0,
//            ArcInst.makeInstanceFull(Schematics.tech.wire_arc, 0.0 /*Schematics.tech.wire_arc.getDefaultLambdaFullWidth()*/,
                    ni.getOnlyPortInst(), ports[pos], null, null, name);
        }
        return null;
    }

    /**
	 * Method to import a Verilog file from disk.
	 * @param lib the library to ready
	 * @return the created library (null on error).
	 */
	protected Library importALibrary(Library lib)
    {
        initKeywordParsing();
        boolean fullOyster = true;
        VerilogData verilogData = parseVerilogInternal(lib.getName(), fullOyster);
        Cell topCell = buildCells(verilogData, lib, fullOyster);
        return (topCell != null) ? lib : null;
    }

    public VerilogData parseVerilog(String[] lines, String verilogName)
    {
        if (openStringsInput(lines))

        {
            System.out.println("Cannot open string set " + verilogName + " as Verilog");
            return null;
        }
        System.out.println("Reading Verilog format " + verilogName);
        initKeywordParsing();
        setProgressValue(0);
        setProgressNote("Reading Verilog format " + verilogName);
        VerilogData verilogData = parseVerilogInternal(verilogName, true);
        System.out.println("Verilog format " + verilogName + " read");
        return verilogData;
    }

    /**
     * Function to parse Verilog file without creating Electric objects.
     * @param file
     * @param simplifyWires
     * @return VerilogData object
     */
    public VerilogData parseVerilog(String file, boolean simplifyWires)
    {
        URL fileURL = TextUtils.makeURLToFile(file);
        if (openTextInput(fileURL))
        {
            System.out.println("Cannot open the Verilog file: " + file);
            return null;
        }
        System.out.println("Reading Verilog file: " + file);
        initKeywordParsing();
        setProgressValue(0);
        setProgressNote("Reading Verilog file:" + file);
        VerilogData verilogData = parseVerilogInternal(file, simplifyWires);
        System.out.println("Verilog file: " + file + " read");