verilogdata.java

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

    public class VerilogInstance implements Serializable
    {
        String name;
        VerilogModule element;
        List<VerilogPortInst> ports = new ArrayList<VerilogPortInst>();
        // number of ports in the instance doesn't necessarily match with number of ports in original elements.

        VerilogInstance(String name, VerilogModule elem)
        {
            this.name = name;
            this.element = elem;
        }

        /**
         * Function to return the name of this instance
         * @return String with the name of the instance
         */
        public String getName() {return name;}

        /**
         * Function to return the module of this instance
         * @return Verilog object
         */
        public VerilogModule getModule() {return element;}

        VerilogPortInst addPortInstance(String name, VerilogPort port)
        {
            VerilogPortInst inst = new VerilogPortInst(name, port);
            ports.add(inst);
            return inst;
        }

        void write()
        {
            System.out.print("\t" + element.name + " " + name + " (");
            int size = ports.size();
//            assert(size == element.getNumPorts());
            for (int i = 0; i < size; i++)
            {
                VerilogPortInst port = ports.get(i);
                System.out.print("." + port.port.name + " (" + port.name + ")");
                if (i < size - 1)
                    System.out.print(", ");
            }
            System.out.println(");");
        }
    }

    /**
         * Compare class for VerilogAll
         */
        private static VerilogAllSort compareVerilogAll = new VerilogAllSort();

        private static class VerilogAllSort implements Comparator<Object>
        {
            public int compare(Object a1, Object a2)
            {
                String name1, name2;
                if (a1 instanceof VerilogInstance)
                    name1 = ((VerilogInstance)a1).getName();
                else if (a1 instanceof VerilogWire)
                    name1 = ((VerilogWire)a1).getName();
                else
                    name1 = ((VerilogPort)a1).getName();
                if (a2 instanceof VerilogInstance)
                    name2 = ((VerilogInstance)a2).getName();
                else if (a2 instanceof VerilogWire)
                    name2 = ((VerilogWire)a2).getName();
                else
                    name2 = ((VerilogPort)a2).getName();
                int cmp = TextUtils.STRING_NUMBER_ORDER.compare(name1, name2);
                return cmp;
            }
        }

    /**
     * Class to represent subcells
     */
    public class VerilogModule implements Serializable
    {
        String name;
        boolean fullInfo; // in case the module information was found in the file
        private List<VerilogWire> wires = new ArrayList<VerilogWire>();
        private Map<String,VerilogPort> ports = new LinkedHashMap<String,VerilogPort>(); // collection of input/output/inout/supply elements, ordering is important
        List<VerilogInstance> instances = new ArrayList<VerilogInstance>();
        boolean primitive; // if this is a primitive instead of a module

        VerilogModule(String name, boolean primitive)
        {
            this.name = name;
            this.fullInfo = false;
        }

        /**
         * Function to mark module as fully read it from the file
         * @param flag
         */
        void setValid(boolean flag) {fullInfo = flag;}

        /**
         * Returns if module is valid, i.e., theinformation was 100% read from the file
         * @return true if is a valid module
         */
        public boolean isValid() {return fullInfo;}

        /**
         * Function returning the name of the module
         * @return String with name of the module
         */
        public String getName() {return name;}

        /**
         * Returns true if this was defined as a 'primitive' instead of
         * a 'module'.
         * @return true if this module was defined as a primitive
         */
        public boolean isPrimitive() { return primitive; }

        /**
         * Returns list of ports and wires sorted by name
         * @return list of ports and wires sorted by namea
         */
        public List<Object> getAllSorted() {

            List<Object> list = new ArrayList<Object>(ports.size() + wires.size());
            list.addAll(ports.values());
            list.addAll(wires);
            Collections.sort(list, compareVerilogAll);
            return list;
        }

        /**
         * Function to return list of VerilogInstance objects in the module.
         * The list is sorted.
         * @return List of VerilogInstance objects
         */
        public List<VerilogInstance> getInstances()
        {
            Collections.sort(instances, compareVerilogInstances);
            return instances;
        }

        /**
         * Function to return list of VerilogWire objects in the module.
         * The list is sorted.
         * @return List of VerilogWire objects
         */
        public List<VerilogWire> getWires()
        {
            Collections.sort(wires, compareVerilogWires);
            return wires;
        }

        /**
         * Function to return collection of VerilogPort objects in the module.
         * The ports are sorted by the name
         * @return Collection of VerilogPort objects
         */
        public Collection<VerilogPort> getPorts()
        {
            List<VerilogPort> list = new ArrayList<VerilogPort>(ports.size());
            list.addAll(ports.values());
            Collections.sort(list, compareVerilogPorts);
            return list;
        }

        /**
         * Function to search an export for a given name
         * @param name export name
         * @return VerilogExport represeting the export
         */
        VerilogPort findPort(String name)
        {
            // In case of large set, better if ports are in a map.
            return ports.get(name);
        }

        /**
         * Function to add a given export to the list
         * @param name name of the new export
         * @param checkClock
         */
        VerilogPort addPort(String name, boolean checkClock)
        {
            if (Job.getDebug())
            {
                if (findPort(name) != null)
                assert(findPort(name) == null);
            }

            PortCharacteristic def = PortCharacteristic.UNKNOWN;
            String lowerName = name.toLowerCase();
            // attempt to get the type based on port name (in,out)
            if (lowerName.startsWith("in"))
                def = PortCharacteristic.IN;
            else if (lowerName.startsWith("out"))
                def = PortCharacteristic.OUT;
            // so far having problems to detect clk signals as input. Only done in case of matching
            // name from the module input
            else if (checkClock && lowerName.endsWith("clk"))  //
                def = PortCharacteristic.CLK;
            VerilogPort export = new VerilogPort(name, def);
            ports.put(name, export);
            return export;
        }

        VerilogInstance addInstance(String name, VerilogModule element)
        {
            VerilogInstance inst = new VerilogInstance(name, element);
            instances.add(inst);
            return inst;
        }

        VerilogWire addWire(String name, String busInfo)
        {
            VerilogData.VerilogWire wire = new VerilogData.VerilogWire(name, busInfo);
            wires.add(wire);
            return wire;
        }

        /**
         * Function to print information in Verilog format. For testing purposes mainly
         */
        void write()
        {
            System.out.print("module " + name + " (");
            Set<String> ports = this.ports.keySet();
            int size = ports.size();
            int count = 0;
            for (String s : ports)
            {
                System.out.print(s);
                if (count < size - 1)
                    System.out.print(", ");
                count++;
            }
            System.out.println(");");
            System.out.println();

            // inputs/outputs/inouts/supplies
            for (VerilogPort e : this.ports.values())
            {
                e.write();
            }
            System.out.println();

            // wires
            for (VerilogWire w : wires)
            {
                w.write();
            }

            // instances
            for (VerilogInstance i : instances)
            {
                i.write();
            }

            System.out.println("endmodule");
            System.out.println();
        }

        /**
         * Simplify wires?: a[1], a[2], a[3] -> a[1:3]
         */
        void simplifyWires()
        {
            Collections.sort(wires, compareVerilogWires);
            int i = 0;
            List<VerilogWire> toDelete = new ArrayList<VerilogWire>();

            while (i < wires.size())
            {
                VerilogWire w = wires.get(i);

                if (w.start == -1)
                {
                    i++;
                    continue; // nothing to do with this one
                }

                // searching for all wire pins with identical root name
                int j, end = w.end;
                List<VerilogWire> toMerge = new ArrayList<VerilogWire>();

                // This algorithm doesn't check for overlapping in pin numbers
                for (j = i+1; j < wires.size(); j++)
                {
                    VerilogWire r = wires.get(j);
                    // in case the element is a wire pin abc[x:y]
                    if (!w.name.equals(r.name))
                    {
                        break; // stop here
                    }
                     // look for next bit
//                    if (r.start != end && r.start != end+1)
//                        break; // stop here

                    end = r.end;
                    toMerge.add(r);
                }
                if (toMerge.size() > 0)
                {
                    // check if pins are conse
                    toDelete.addAll(toMerge);
                    w.end = end;
                }
                i = j;
            }
            wires.removeAll(toDelete);
        }
    }

    private static VerilogWireSort compareVerilogWires = new VerilogWireSort();

    private static class VerilogWireSort implements Comparator<VerilogWire>
    {
        public int compare(VerilogWire a1, VerilogWire a2)
        {
            int diff = TextUtils.STRING_NUMBER_ORDER.compare(a1.name, a2.name);
//            int diff = (a1.name.compareTo(a2.name));
            if (diff == 0) // identical
            {
                diff = a1.start - a2.start;
                if (diff == 0) // try with end pins
                {
                    diff = a1.end - a2.end;
                    assert(diff!=0); // can't have identical wires
                }
            }
            return (diff);
        }
    }
}