redgeneric180.jelib

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

NGround|gnd@0||0|-12.5|3|4||
IinvHT;1{ic}|invHT@0||16|10.5||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(PT)Sstrong0|ATTR_drive1(PT)Sstrong1
Ngeneric:Invisible-Pin|pin@0||26.5|-10|0|0|||ART_message(D5G2;)S[X is drive strength,P drive strength is twice N strength]
Ngeneric:Invisible-Pin|pin@1||1|17|0|0|||ART_message(D5G2;)S[P to N width ratio is 4 to 1]
NWire_Pin|pin@2||-4|0|0.5|0.5||
NWire_Pin|pin@3||-4|-6|0.5|0.5||
NWire_Pin|pin@4||-4|6|0.5|0.5||
NWire_Pin|pin@5||0|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@6||0|19|0|0|||ART_message(D5G2;)S[HI-threshold fixed-size (non-LE) inverter]
Ngeneric:Invisible-Pin|pin@7||-1|24|0|0|||ART_message(D5G6;)S[invHT]
NPower|pwr@0||0|12.5|3|3||
Awire|net@0||0|900|pwr@0||0|12.5|PMOS@0|s|0|8
Awire|net@1||0|1800|pin@4||-4|6|PMOS@0|g|-3|6
Awire|net@2||0|2700|pin@5||0|0|PMOS@0|d|0|4
Awire|net@3||0|2700|gnd@0||0|-10.5|NMOS@0|s|0|-8
Awire|net@4||0|900|pin@5||0|0|NMOS@0|d|0|-4
Awire|net@5||0|1800|pin@3||-4|-6|NMOS@0|g|-3|-6
Awire|net@6||0|0|pin@2||-4|0|conn@0|y|-9|0
Awire|net@7||0|2700|pin@3||-4|-6|pin@2||-4|0
Awire|net@8||0|2700|pin@2||-4|0|pin@4||-4|6
Awire|net@9||0|0|conn@1|a|6|0|pin@5||0|0
Ein|D5G2;|conn@0|a|I
Eout|D5G2;|conn@1|y|O
X

# Cell invK{ic}
CinvK;1{ic}|artwork|1021415734000|1048541126000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-2|0|1|1|||ART_color()I10
NOpened-Thicker-Polygon|art@2||-0.5|0|0.5|1|||ART_color()I10|trace()V[-0.25/0.5,-0.25/-0.5,-0.25/0,0.25/0.5,-0.25/0,0.25/-0.5]
Nschematic:Bus_Pin|pin@0||2.5|0|0|0||
NPin|pin@1||1.5|0|1|1||W
NPin|pin@2||2.5|0|0|0||W
Nschematic:Bus_Pin|pin@3||-2.5|0|0|0||
NPin|pin@4||-1.5|-2|1|1||W
NPin|pin@5||-1.5|2|1|1||W
NPin|pin@6||1.5|0|1|1||W
AThicker|net@0||0|FS0|pin@2||2.5|0|pin@1||1.5|0|ART_color()I10
AThicker|net@1||0|FS3263|pin@6||1.5|0|pin@5||-1.5|2|ART_color()I10
AThicker|net@2||0|FS336|pin@6||1.5|0|pin@4||-1.5|-2|ART_color()I10
AThicker|net@3||0|FS2700|pin@4||-1.5|-2|pin@5||-1.5|2|ART_color()I10
Ein|D5G1;|pin@3||I
Eout|D5G1;|pin@0||O
X

# Cell invK{sch}
CinvK;1{sch}|schematic|1021415734000|1084347245000||ATTR_Delay(D5G1;HNOJPX-14;Y-6.5;)S@Delay|ATTR_X(D5G1;HNPX-14;Y-5.5;)I1|ATTR_drive0(D5G1;HNPTX-14;Y-7.5;)Sweak0|ATTR_drive1(D5G1;HNPTX-14;Y-8.5;)Sweak1|ATTR_verilog_template(D5G1;NTX30;Y-15;)Snot ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(in));|prototype_center()I[0,0]
INMOSwk;1{ic}|NMOSwk@0||2|-5||E|D0G4;|ATTR_Delay(D5G1;NOJPTX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IPMOSwk;1{ic}|PMOSwk@0||2|6||E|D0G4;|ATTR_Delay(D5G1;NOJPTX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||8|0|4|2||
NOff-Page|conn@1||-11|0|4|2||
NGround|gnd@0||2|-12|3|4||
IinvK;1{ic}|invK@0||18.5|12||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-2;)I100|ATTR_LEKEEPER(T)I1|ATTR_LEPARALLGRP()I-1|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sweak0|ATTR_drive1(P)Sweak1|ATTR_su()I-1
Ngeneric:Invisible-Pin|pin@0||-1|18|0|0|||ART_message(D5G2;)S[LO threshold fixed-size keeper inverter]
Ngeneric:Invisible-Pin|pin@1||-1|23.5|0|0|||ART_message(D5G6;)S[invK]
Ngeneric:Invisible-Pin|pin@2||-2|16|0|0|||ART_message(D5G2;)S[P to N width ratio is 2 to 1]
Ngeneric:Invisible-Pin|pin@3||28.5|-10.5|0|0|||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
NWire_Pin|pin@4||-2|-5|1|1||
NWire_Pin|pin@5||-2|6|1|1||
NWire_Pin|pin@6||-2|0|0.5|0.5||
NWire_Pin|pin@7||2|0|0.5|0.5||
NPower|pwr@0||2|11.5|3|3||
Awire|net@0||0|2700|PMOSwk@0|s|2|8|pwr@0||2|11.5
Awire|net@1||0|0|PMOSwk@0|g|-1|6|pin@5||-2|6
Awire|net@2||0|2700|pin@7||2|0|PMOSwk@0|d|2|4
Awire|net@3||0|2700|gnd@0||2|-10|NMOSwk@0|s|2|-7
Awire|net@4||0|2700|NMOSwk@0|d|2|-3|pin@7||2|0
Awire|net@5||0|0|NMOSwk@0|g|-1|-5|pin@4||-2|-5
Awire|net@6||0|2700|pin@4||-2|-5|pin@6||-2|0
Awire|net@7||0|2700|pin@6||-2|0|pin@5||-2|6
Awire|net@8||0|0|conn@0|a|6|0|pin@7||2|0
Awire|net@9||0|1800|conn@1|y|-9|0|pin@6||-2|0
Ein|D5G2;|conn@1|a|I
Eout|D5G2;|conn@0|y|O
X

# Cell invKV{ic}
CinvKV;1{ic}|artwork|1021415734000|1047066174000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOpened-Thicker-Polygon|art@1||-0.5|0.5|0.5|1|||ART_color()I10|trace()V[-0.25/0.5,-0.25/-0.5,-0.25/0,0.25/0.5,-0.25/0,0.25/-0.5]
NThick-Circle|art@2||-2|0|1|1|||ART_color()I10
NOpened-Thicker-Polygon|art@3||-0.5|-0.75|0.5|1|||ART_color()I10|trace()V[-0.25/0.5,0/-0.5,0.25/0.5]
NPin|pin@0||1.5|0|1|1||W
NPin|pin@1||-1.5|2|1|1||W
NPin|pin@2||-1.5|-2|1|1||W
NPin|pin@3||2.5|0|0|0||W
NPin|pin@4||1.5|0|1|1||W
Nschematic:Bus_Pin|pin@5||2.5|0|0|0||
Nschematic:Bus_Pin|pin@6||-2.5|0|0|0||
AThicker|net@0||0|FS2700|pin@2||-1.5|-2|pin@1||-1.5|2|ART_color()I10
AThicker|net@1||0|FS336|pin@0||1.5|0|pin@2||-1.5|-2|ART_color()I10
AThicker|net@2||0|FS3263|pin@0||1.5|0|pin@1||-1.5|2|ART_color()I10
AThicker|net@3||0|FS0|pin@3||2.5|0|pin@4||1.5|0|ART_color()I10
Ein|D5G1;|pin@6||I
Eout|D5G1;|pin@5||O
X

# Cell invKV{sch}
CinvKV;1{sch}|schematic|1021415734000|1053725511000||ATTR_Delay(D5G1;HNPX-11.5;Y-5.5;)I100|ATTR_XN(D5G1;HNPX-11.5;Y-3.5;)I1|ATTR_XP(D5G1;HNPX-11.5;Y-4.5;)I1|ATTR_drive0(D5G1;HNPTX-11;Y-6.5;)Sweak0|ATTR_drive1(D5G1;HNPTX-11;Y-7.5;)Sweak1|ATTR_verilog_template(D5G1;NTX24.5;Y-13;)Snot ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(in));|prototype_center()I[0,0]
INMOSwk;1{ic}|NMOSwk@0||0|-6||E|D0G4;|ATTR_Delay(D5G1;NOJPTX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@XN|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IPMOSwk;1{ic}|PMOSwk@0||0|6||E|D0G4;|ATTR_Delay(D5G1;NOJPTX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@XP|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||-11|0|4|2||
NOff-Page|conn@1||8|0|4|2||
NGround|gnd@0||0|-11|3|4||
IinvKV;1{ic}|invKV@0||21.5|9||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-4;)I100|ATTR_XN(D5G1.5;NPX1.5;Y-2.25;)I1|ATTR_XP(D5G1.5;NPX1.5;Y1.75;)I1|ATTR_drive0(PT)Sweak0|ATTR_drive1(PT)Sweak1
Ngeneric:Invisible-Pin|pin@0||26|-7.5|0|0|||ART_message(D5G2;)S[X is drive strength,"P and N drive strengths are XP, XN"]
NWire_Pin|pin@1||-4|-6|0.5|0.5||
NWire_Pin|pin@2||-4|6|0.5|0.5||
NWire_Pin|pin@3||0|0|0.5|0.5||
NWire_Pin|pin@4||-4|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@5||-0.5|17|0|0|||ART_message(D5G6;)S[invKV]
Ngeneric:Invisible-Pin|pin@6||-1|13.5|0|0|||ART_message(D5G2;)S[Two parameter variable ratio keeper]
NPower|pwr@0||0|10.5|3|3||
Awire|net@0||0|1800|pin@1||-4|-6|NMOSwk@0|g|-3|-6
Awire|net@1||0|2700|PMOSwk@0|s|0|8|pwr@0||0|10.5
Awire|net@2||0|1800|pin@2||-4|6|PMOSwk@0|g|-3|6
Awire|net@3||0|2700|pin@3||0|0|PMOSwk@0|d|0|4
Awire|net@4||0|900|NMOSwk@0|s|0|-8|gnd@0||0|-9
Awire|net@5||0|2700|NMOSwk@0|d|0|-4|pin@3||0|0
Awire|net@6||0|1800|conn@0|y|-9|0|pin@4||-4|0
Awire|net@7||0|0|conn@1|a|6|0|pin@3||0|0
Awire|net@8||0|2700|pin@1||-4|-6|pin@4||-4|0
Awire|net@9||0|2700|pin@4||-4|0|pin@2||-4|6
Ein|D5G2;|conn@0|a|I
Eout|D5G2;|conn@1|y|O
X

# Cell invLT{ic}
CinvLT;1{ic}|artwork|1021415734000|1046472665000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||2|0|1|1|||ART_color()I10
NOpened-Thicker-Polygon|art@2||-0.25|0|0.5|1|||ART_color()I10|trace()V[-0.25/0.5,-0.25/-0.5,0.25/-0.5]
Nschematic:Bus_Pin|pin@0||2.5|0|0|0||
Nschematic:Bus_Pin|pin@1||-2.5|0|0|0||
NPin|pin@2||-1.5|-2|1|1||W
NPin|pin@3||-1.5|2|1|1||W
NPin|pin@4||-2.5|0|0|0||W
NPin|pin@5||-1.5|0|1|1||W
NPin|pin@6||1.5|0|1|1||W
AThicker|net@0||0|FS3263|pin@6||1.5|0|pin@3||-1.5|2|ART_color()I10
AThicker|net@1||0|FS336|pin@6||1.5|0|pin@2||-1.5|-2|ART_color()I10
AThicker|net@2||0|FS2700|pin@2||-1.5|-2|pin@3||-1.5|2|ART_color()I10
AThicker|net@3||0|FS0|pin@5||-1.5|0|pin@4||-2.5|0|ART_color()I10
Ein|D5G1;|pin@1||I
Eout|D5G1;|pin@0||O
X

# Cell invLT{sch}
CinvLT;1{sch}|schematic|1021415734000|1060030654000||ATTR_Delay(D5G1;HNPX-12;Y-5;)I100|ATTR_X(D5G1;HNPX-12;Y-4;)I1|ATTR_drive0(D5G1;HNPTX-12;Y-6;)Sstrong0|ATTR_drive1(D5G1;HNPTX-12;Y-7;)Sstrong1|ATTR_verilog_template(D5G1;NTX23;Y-13;)Snot ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(in));|prototype_center()I[0,0]
INMOS;1{ic}|NMOS@0||0|-6||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*2.0|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IPMOS;1{ic}|PMOS@0||0|6||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||11|0|4|2||
NOff-Page|conn@1||-11.5|0|4|2||
NGround|gnd@0||0|-12.5|3|4||
IinvLT;1{ic}|invLT@0||16|10.5||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(PT)Sstrong0|ATTR_drive1(PT)Sstrong1
NWire_Pin|pin@0||-4|0|0.5|0.5||
NWire_Pin|pin@1||0|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@2||-1|24|0|0|||ART_message(D5G6;)S[invLT]
Ngeneric:Invisible-Pin|pin@3||0|19|0|0|||ART_message(D5G2;)S[LO-threshold fixed-size (non-LE) inverter]
NWire_Pin|pin@4||-4|6|0.5|0.5||
NWire_Pin|pin@5||-4|-6|0.5|0.5||
Ngeneric:Invisible-Pin|pin@6||0.5|17|0|0|||ART_message(D5G2;)S[This is a 2 to 2 width ratio inverter]
Ngeneric:Invisible-Pin|pin@7||24|-9|0|0|||ART_message(D5G2;)S[X is drive strength,N drive strength is twice P strength]
NPower|pwr@0||0|12.5|3|3||
Awire|net@0||0|0|pin@0||-4|0|conn@1|y|-9.5|0
Awire|net@1||0|900|pin@4||-4|6|pin@0||-4|0
Awire|net@2||0|900|pin@0||-4|0|pin@5||-4|-6
Awire|net@3||0|1800|pin@1||0|0|conn@0|a|9|0
Awire|net@4||0|2700|NMOS@0|d|0|-4|pin@1||0|0
Awire|net@5||0|2700|pin@1||0|0|PMOS@0|d|0|4
Awire|net@6||0|900|pwr@0||0|12.5|PMOS@0|s|0|8
Awire|net@7||0|1800|pin@4||-4|6|PMOS@0|g|-3|6
Awire|net@8||0|2700|gnd@0||0|-10.5|NMOS@0|s|0|-8
Awire|net@9||0|1800|pin@5||-4|-6|NMOS@0|g|-3|-6
Ein|D5G2;|conn@1|a|I
Eout|D5G2;|conn@0|y|O
X

# Cell invV{ic}
CinvV;1{ic}|artwork|1021415734000|1043179065000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||2|0|1|1|||ART_color()I10
NOpened-Thicker-Polygon|art@2||-0.5|0|0.5|1|||ART_color()I10|trace()V[-0.25/0.5,0/-0.5,0.25/0.5]
Nschematic:Bus_Pin|pin@0||-2.5|0|0|0||
Nschematic:Bus_Pin|pin@1||2.5|0|0|0||
NPin|pin@2||-1.5|-2|1|1||W
NPin|pin@3||-1.5|2|1|1||W
NPin|pin@4||-2.5|0|0|0||W
NPin|pin@5||-1.5|0|1|1||W
NPin|pin@6||1.5|0|1|1||W
AThicker|net@0||0|FS0|pin@5||-1.5|0|pin@4||-2.5|0|ART_color()I10
AThicker|net@1||0|FS3263|pin@6||1.5|0|pin@3||-1.5|2|ART_color()I10
AThicker|net@2||0|FS336|pin@6||1.5|0|pin@2||-1.5|-2|ART_color()I10
AThicker|net@3||0|FS2700|pin@2||-1.5|-2|pin@3||-1.5|2|ART_color()I10
Ein|D5G1;|pin@0||I
Eout|D5G1;|pin@1||O
X

# Cell invV{sch}
CinvV;1{sch}|schematic|1021415734000|1056432785000||ATTR_Delay(D5G1;HNPX-12;Y-7;)I100|ATTR_XN(D5G1;HNPX-12;Y-5;)I1|ATTR_XP(D5G1;HNPX-12;Y-6;)I1|ATTR_drive0(D5G1;HNPTX-12;Y-8;)Sstrong0|ATTR_drive1(D5G1;HNPTX-12;Y-9;)Sstrong1|ATTR_verilog_template(D5G1;NTX19.5;Y-16;)Snot ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(in));|prototype_center()I[0,0]
INMOS;1{ic}|NMOS@0||0|-6||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@XN|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IPMOS;1{ic}|PMOS@0||0|6||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@XP|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||7|0|4|2||
NOff-Page|conn@1||-12|0|4|2||
NGround|gnd@0||0|-12|3|4||
IinvV;1{ic}|invV@0||24|10.5||E|D0G4;|ATTR_Delay(D5G1;NPTX1.5;Y-4;)I100|ATTR_XN(D5G1.5;NPX1.75;Y-2.5;)I1|ATTR_XP(D5G1.5;NPX1.75;Y2;)I1|ATTR_drive0(PT)Sstrong0|ATTR_drive1(PT)Sstrong1
Ngeneric:Invisible-Pin|pin@0||0.5|17.5|0|0|||ART_message(D5G2;)S[two-parameter variable ratio inverter]
Ngeneric:Invisible-Pin|pin@1||-0.5|21.5|0|0|||ART_message(D5G6;)S[invV]
NWire_Pin|pin@2||0|0|0.5|0.5||
NWire_Pin|pin@3||-5|0|0.5|0.5||
NWire_Pin|pin@4||-5|-6|0.5|0.5||
NWire_Pin|pin@5||-5|6|0.5|0.5||
Ngeneric:Invisible-Pin|pin@6||28|-11.5|0|0|||ART_message(D5G2;)S[X is drive strength,"P and N drive strengths are XP, XN"]
NPower|pwr@0||0|10.5|3|3||
Awire|net@0||0|900|NMOS@0|s|0|-8|gnd@0||0|-10
Awire|net@1||0|900|pin@2||0|0|NMOS@0|d|0|-4
Awire|net@2||0|1800|pin@4||-5|-6|NMOS@0|g|-3|-6
Awire|net@3||0|2700|PMOS@0|s|0|8|pwr@0||0|10.5
Awire|net@4||0|1800|pin@5||-5|6|PMOS@0|g|-3|6
Awire|net@5||0|2700|pin@2||0|0|PMOS@0|d|0|4
Awire|net@6||0|1800|pin@2||0|0|conn@0|a|5|0
Awire|net@7||0|0|pin@3||-5|0|conn@1|y|-10|0
Awire|net@8||0|2700|pin@4||-5|-6|pin@3||-5|0
Awire|net@9||0|2700|pin@3||-5|0|pin@5||-5|6
Ein|D5G2;|conn@1|a|I
Eout|D5G2;|conn@0|y|O
X

# Cell invVn{ic}
CinvVn;1{ic}|artwork|1021415734000|1056416438000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||2|0|1|1|||ART_color()I10
NOpened-Thicker-Polygon|art@2||-0.5|0|0.5|1|||ART_color()I10|trace()V[-0.25/0.5,0/-0.5,0.25/0.5]
NOpened-Thicker-Polygon|art@3||0.25|-0.12|0.5|0.75|||ART_color()I10|trace()V[-0.25/-0.375,-0.25/0.375,0.25/-0.375,0.25/0.375]
Nschematic:Bus_Pin|pin@0||-2.5|0|0|0||
Nschematic:Bus_Pin|pin@1||2.5|0|0|0||
NPin|pin@2||-1.5|-2|1|1||W
NPin|pin@3||-1.5|2|1|1||W
NPin|pin@4||-2.5|0|0|0||W
NPin|pin@5||-1.5|0|1|1||W
NPin|pin@6||1.5|0|1|1||W
AThicker|net@0||0|FS0|pin@5||-1.5|0|pin@4||-2.5|0|ART_color()I10
AThicker|net@1||0|FS3263|pin@6||1.5|0|pin@3||-1.5|2|ART_color()I10
AThicker|net@2||0|FS336|pin@6||1.5|0|pin@2||-1.5|-2|ART_color()I10
AThicker|net@3||0|FS2700|pin@2||-1.5|-2|pin@3||-1.5|2|ART_color()I10
Ein|D5G1;|pin@0||I
Eout|D5G1;|pin@1||O
X

# Cell invVn{sch}
CinvVn;1{sch}|schematic|1021415734000|1059582248000||ATTR_Delay(D5G1;HNPX-15.5;Y-7.5;)I100|ATTR_NPdrvR(D5G1;HNPX-15.5;Y-6.5;)I1|ATTR_X(D5G1;HNPX-15.5;Y-5.5;)I1|ATTR_drive0(D5G1;HNPTX-15.5;Y-8.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-15.5;Y-9.5;)Sstrong1|ATTR_verilog_template(D5G1;NTX18.5;Y-19.5;)Snot ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(in));|prototype_center()I[0,0]
INMOS;1{ic}|NMOS@0||0|-6||E|D0G4;|ATTR_Delay(D5G1;NOJPTX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*@NPdrvR|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IPMOS;1{ic}|PMOS@0||0|6||E|D0G4;|ATTR_Delay(D5G1;NOJPTX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3;)S@X|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||7|0|4|2||
NOff-Page|conn@1||-12|0|4|2||
NGround|gnd@0||0|-12|3|4||
IinvVn;1{ic}|invVn@0||26.75|6||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-3;)I100|ATTR_NPdrvR(D5G1;NPTX2;Y-2;)I1|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(PT)Sstrong0|ATTR_drive1(PT)Sstrong1
Ngeneric:Invisible-Pin|pin@0||0.5|17.5|0|0|||ART_message(D5G2;)S[variable ratio inverter]
Ngeneric:Invisible-Pin|pin@1||-0.5|22|0|0|||ART_message(D5G6;)S[invVn]
NWire_Pin|pin@2||0|0|0.5|0.5||
NWire_Pin|pin@3||-5|0|0.5|0.5||
NWire_Pin|pin@4||-5|-6|0.5|0.5||
NWir