redgeneric180.jelib

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

Awire|net@11||0|900|pin@6||0|0|NMOS@0|d|0|-4
Awire|net@12||0|0|conn@2|a|6|0|pin@6||0|0
Awire|net@15||0|1800|conn@0|y|-7.5|-6|NMOS@0|g|-3|-6
Awire|net@16||0|1800|conn@1|y|-8|6|PMOS@0|g|-3|6
Ein[n]|D5G2;|conn@0|a|I
Ein[p]|D5G2;|conn@1|a|I
Eout|D5G2;|conn@2|y|O
X

# Cell inv2iV{ic}
Cinv2iV;1{ic}|artwork|1021415734000|1056431142000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||2|0|1|1|||ART_color()I10
NThick-Circle|art@2||-1|1|1|1|||ART_color()I10
NOpened-Thicker-Polygon|art@3||-0.25|0|0.5|1|||ART_color()I10|trace()V[-0.25/0.5,0/-0.5,0.25/0.5]
Nschematic:Bus_Pin|pin@0||-2.5|-1|0|0||
Nschematic:Bus_Pin|pin@1||2.5|0|0|0||
Nschematic:Bus_Pin|pin@2||-2.5|1|0|0||
NPin|pin@3||-1.5|-2|1|1||W
NPin|pin@4||-1.5|2|1|1||W
NPin|pin@5||-2.5|-1|0|0||W
NPin|pin@6||-1.5|-1|1|1||W
NPin|pin@7||1.5|0|1|1||W
NPin|pin@8||-1.5|1|1|1||W
NPin|pin@9||-2.5|1|0|0||W
AThicker|net@0||0|FS0|pin@6||-1.5|-1|pin@5||-2.5|-1|ART_color()I10
AThicker|net@1||0|FS3263|pin@7||1.5|0|pin@4||-1.5|2|ART_color()I10
AThicker|net@2||0|FS336|pin@7||1.5|0|pin@3||-1.5|-2|ART_color()I10
AThicker|net@3||0|FS2700|pin@3||-1.5|-2|pin@4||-1.5|2|ART_color()I10
AThicker|net@4||0|FS0|pin@8||-1.5|1|pin@9||-2.5|1|ART_color()I10
Ein[n]|D5G1;|pin@0||I
Ein[p]|D5G1;|pin@2||I
Eout|D5G1;|pin@1||O
X

# Cell inv2iV{sch}
Cinv2iV;1{sch}|schematic|1021415734000|1059582248000||ATTR_Delay(D5G1;HNPX-16;Y-12;)I100|ATTR_XN(D5G1;HNPX-16;Y-10;)I1|ATTR_XP(D5G1;HNPX-16;Y-11;)I1|ATTR_drive0(D5G1;HNPTX-16;Y-13;)Sstrong0|ATTR_drive1(D5G1;HNPTX-16;Y-14;)Sstrong1|prototype_center()I[0,0]
INMOS;1{ic}|NMOS@0||0|-6||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@XN|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IPMOS;1{ic}|PMOS@0||0|6||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@XP|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||-12|-6|4|2||
NOff-Page|conn@1||7|0|4|2||
NOff-Page|conn@2||-12|6|4|2||
NGround|gnd@0||0|-12|3|4||
Iinv2iV;1{ic}|inv2iV@0||18.5|9.5||E|D0G4;|ATTR_Delay(D5G1;NPTX1.5;Y-4;)I100|ATTR_XN(D5G1.5;NPX1.5;Y-2.5;)I1|ATTR_XP(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
NWire_Pin|pin@0||0|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@1||-1.5|21|0|0|||ART_message(D5G6;)S[inv2iV]
Ngeneric:Invisible-Pin|pin@2||-0.5|16.5|0|0|||ART_message(D5G2;)S[two-parameter two-input variable ratio inverter]
Ngeneric:Invisible-Pin|pin@3||25|-12.5|0|0|||ART_message(D5G2;)S[X is drive strength,"P and N drive strengths are XP, XN"]
NPower|pwr@0||0|10.5|3|3||
Awire|net@0||0|0|NMOS@0|g|-3|-6|conn@0|y|-10|-6
Awire|net@1||0|0|PMOS@0|g|-3|6|conn@2|y|-10|6
Awire|net@2||0|0|conn@1|a|5|0|pin@0||0|0
Awire|net@3||0|900|pin@0||0|0|NMOS@0|d|0|-4
Awire|net@4||0|2700|pin@0||0|0|PMOS@0|d|0|4
Awire|net@5||0|900|NMOS@0|s|0|-8|gnd@0||0|-10
Awire|net@6||0|2700|PMOS@0|s|0|8|pwr@0||0|10.5
Ein[n]|D5G2;|conn@0|a|I
Ein[p]|D5G2;|conn@2|a|I
Eout|D5G2;|conn@1|y|O
X

# Cell invCLK{ic}
CinvCLK;1{ic}|artwork|1021415734000|1080149268000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOpened-Thicker-Polygon|art@1||-0.25|0|0.5|1|||ART_color()I10|trace()V[0.25/-0.5,-0.25/-0.5,-0.25/0.5]
NOpened-Thicker-Polygon|art@2||-1|0|0.5|1|||ART_color()I10|trace()V[0.25/-0.5,-0.25/-0.5,-0.25/0.5,0.25/0.5]
NThick-Circle|art@3||2|0|1|1|||ART_color()I10
NOpened-Thicker-Polygon|art@4||0.5|0|0.5|1|||ART_color()I10|trace()V[-0.25/-0.5,-0.25/0.5,-0.25/0,0.25/0.5,-0.25/0,0.25/-0.5]
Nschematic:Bus_Pin|pin@0||2.5|0|0|0||
Nschematic:Bus_Pin|pin@1||-2.5|0|0|0||
NPin|pin@2||-1.5|-2|1|1||W
NPin|pin@3||-1.5|2|1|1||W
NPin|pin@4||-2.5|0|0|0||W
NPin|pin@5||-1.5|0|1|1||W
NPin|pin@6||1.5|0|1|1||W
AThicker|net@0||0|FS3263|pin@6||1.5|0|pin@3||-1.5|2|ART_color()I10
AThicker|net@1||0|FS336|pin@6||1.5|0|pin@2||-1.5|-2|ART_color()I10
AThicker|net@2||0|FS2700|pin@2||-1.5|-2|pin@3||-1.5|2|ART_color()I10
AThicker|net@3||0|FS0|pin@5||-1.5|0|pin@4||-2.5|0|ART_color()I10
Ein|D5G1;|pin@1||I
Eout|D5G1;|pin@0||O
X

# Cell invCLK{sch}
CinvCLK;1{sch}|schematic|1021415734000|1084347287000||ATTR_Delay(D5G1;HNPX-12;Y-5.5;)I100|ATTR_X(D5G1;HNPX-12;Y-4.5;)I1|ATTR_drive0(D5G1;HNPTX-12;Y-6.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-12;Y-7.5;)Sstrong1|ATTR_verilog_template(D5G1;NTX28.5;Y-15;)Snot ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(in));|prototype_center()I[0,0]
INMOS;1{ic}|NMOS@0||0|-6||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IPMOS;1{ic}|PMOS@0||0|6||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*1.5|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||8|0|4|2||
NOff-Page|conn@1||-11|0|4|2||
NGround|gnd@0||0|-12.5|3|4||
IinvCLK;1{ic}|invCLK@0||16|10.5||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(PT)Sstrong0|ATTR_drive1(PT)Sstrong1
Ngeneric:Invisible-Pin|pin@0||-0.5|19|0|0|||ART_message(D5G2;)S[intended for driving clock circuits - gives nearly equal rise/fall]
Ngeneric:Invisible-Pin|pin@1||-1|28|0|0|||ART_message(D5G6;)S[invCLK]
Ngeneric:Invisible-Pin|pin@2||0|23|0|0|||ART_message(D5G2;)S[medium HI-threshold fixed-size (non-LE) inverter]
NWire_Pin|pin@3||0|0|0.5|0.5||
NWire_Pin|pin@4||-4|6|0.5|0.5||
NWire_Pin|pin@5||-4|-6|0.5|0.5||
NWire_Pin|pin@6||-4|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@7||1|21|0|0|||ART_message(D5G2;)S[P to N width ratio is 3 to 1]
Ngeneric:Invisible-Pin|pin@8||28|-10.5|0|0|||ART_message(D5G2;)S[X is drive strength,P drive strength is twice N strength]
NPower|pwr@0||0|12.5|3|3||
Awire|net@0||0|0|conn@0|a|6|0|pin@3||0|0
Awire|net@1||0|2700|pin@6||-4|0|pin@4||-4|6
Awire|net@2||0|2700|pin@5||-4|-6|pin@6||-4|0
Awire|net@3||0|0|pin@6||-4|0|conn@1|y|-9|0
Awire|net@4||0|1800|pin@5||-4|-6|NMOS@0|g|-3|-6
Awire|net@5||0|900|pin@3||0|0|NMOS@0|d|0|-4
Awire|net@6||0|2700|gnd@0||0|-10.5|NMOS@0|s|0|-8
Awire|net@7||0|2700|pin@3||0|0|PMOS@0|d|0|4
Awire|net@8||0|1800|pin@4||-4|6|PMOS@0|g|-3|6
Awire|net@9||0|900|pwr@0||0|12.5|PMOS@0|s|0|8
Ein|D5G2;|conn@1|a|I
Eout|D5G2;|conn@0|y|O
X

# Cell invCTLn{ic}
CinvCTLn;1{ic}|artwork|993434516000|1060361787000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||2|0|1|1|||ART_color()I10
Ngeneric:Invisible-Pin|pin@0||-2.5|0|0|0||
Ngeneric:Invisible-Pin|pin@1||2.5|0|0|0||
NPin|pin@2||-1.5|2|0.5|0.5||W
NPin|pin@3||-1.5|-2|0.5|0.5||W
NPin|pin@4||1.5|0|0.5|0.5||W
Ngeneric:Invisible-Pin|pin@5||0|0|0|0|||ART_message(D5G1.5;)S[CTLn]
Ngeneric:Invisible-Pin|pin@6||0|-2|0|0||
NPin|pin@7||0|-2|1|1||W
NPin|pin@8||0|-1|1|1||W
NPin|pin@9||-2.5|0|1|1|R|W
NPin|pin@10||-1.5|0|1|1|R|W
AThicker|net@0||0|FS900|pin@2||-1.5|2|pin@3||-1.5|-2|ART_color()I10
AThicker|net@1||0|FS3263|pin@4||1.5|0|pin@2||-1.5|2|ART_color()I10
AThicker|net@2||0|FS2136|pin@3||-1.5|-2|pin@4||1.5|0|ART_color()I10
AThicker|net@3||0|FS900|pin@8||0|-1|pin@7||0|-2|ART_color()I10
AThicker|net@4||0|FS1800|pin@9||-2.5|0|pin@10||-1.5|0|ART_color()I10
Ectl|D5G2;|pin@6||I
Ein|D5G2;|pin@0||I
Eout|D5G2;|pin@1||O
X

# Cell invCTLn{sch}
CinvCTLn;1{sch}|schematic|993433994000|1060361843000||ATTR_Delay(D5G2;HNPX-21.5;Y1;)I100|ATTR_X(D5G2;HNPX-21.5;Y4;)I1|ATTR_sloDelay(D5G2;HNPX-22;Y-1.5;)I175|prototype_center()I[0,0]
INMOS;1{ic}|NMOS@0||0|0.5||E|D0G4;|ATTR_Delay(D5G1;NOJPTX3.5;Y-2;)S@sloDelay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*2.0|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
INMOSwk;1{ic}|NMOSwk@0||0|9.5||E|D0G4;|ATTR_Delay(D5G1;NOJPTX3.5;Y-2;)S@sloDelay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*2.0|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IPMOS;1{ic}|PMOS@0||0|22||E|D0G4;|ATTR_Delay(D5G1;NOJPTX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||12.5|16|4|2||
NOff-Page|conn@1||-12|16|4|2||
NOff-Page|conn@2||-13|9.5|4|2||
NGround|gnd@0||0|-6.5|3|4||
IinvCTLn;1{ic}|invCTLn@0||15|27.75||E|D0G4;|ATTR_Delay(D5G1;NPX4.5;Y-1.5;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I2|ATTR_sloDelay(D5G1;NPX4.5;Y-3;)I175
NWire_Pin|pin@0||-5|16|0.5|0.5||
NWire_Pin|pin@1||0|16|0.5|0.5||
Ngeneric:Invisible-Pin|pin@2||0|33|0|0|||ART_message(D5G3;)S[invCTLn]
NWire_Pin|pin@3||-5|22|0.5|0.5||
NWire_Pin|pin@4||-2.5|22|0.5|0.5||
NWire_Pin|pin@5||0|20.5|0.5|0.5||
NWire_Pin|pin@6||-5|0.5|0.5|0.5||
NPower|pwr@0||0|28|3|3||
Awire|net@0||0|0|pin@0||-5|16|conn@1|y|-10|16
Awire|net@1||0|1800|pin@1||0|16|conn@0|a|10.5|16|SIM_verilog_wire_type(D5G1;)Strireg
Awire|net@2||0|900|pin@3||-5|22|pin@0||-5|16
Awire|net@3||0|1800|pin@3||-5|22|pin@4||-2.5|22
Awire|net@4||0|2700|PMOS@0|d|0|20|pin@5||0|20.5
Awire|net@5||0|900|pwr@0||0|28|PMOS@0|s|0|24
Awire|net@6||0|1800|PMOS@0|g|-3|22|pin@4||-2.5|22
Awire|net@7||0|1800|pin@6||-5|0.5|NMOS@0|g|-3|0.5
Awire|net@8||0|900|NMOS@0|s|0|-1.5|gnd@0||0|-4.5
Awire|net@9||0|2700|pin@6||-5|0.5|pin@0||-5|16
Awire|net@10||0|900|pin@1||0|16|NMOSwk@0|d|0|11.5
Awire|net@11||0|2700|NMOS@0|d|0|2.5|NMOSwk@0|s|0|7.5
Awire|net@12||0|2700|pin@1||0|16|PMOS@0|d|0|20
Awire|net@13||0|0|NMOSwk@0|g|-3|9.5|conn@2|y|-11|9.5
Ectl|D5G2;X-4;|conn@2|y|I
Ein|D5G2;|conn@1|a|I
Eout|D5G2;|conn@0|y|O
X

# Cell invCTLp{ic}
CinvCTLp;1{ic}|artwork|993434516000|1061317969000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||0|-1.5|1|1|||ART_color()I10
NThick-Circle|art@2||2|0|1|1|||ART_color()I10
NPin|pin@0||-1.5|0|1|1|R|W
NPin|pin@1||-2.5|0|1|1|R|W
Ngeneric:Invisible-Pin|pin@2||0|-2|0|0||
Ngeneric:Invisible-Pin|pin@3||0|0|0|0|||ART_message(D5G1.5;)S[CTLp]
NPin|pin@4||1.5|0|0.5|0.5||W
NPin|pin@5||-1.5|-2|0.5|0.5||W
NPin|pin@6||-1.5|2|0.5|0.5||W
Ngeneric:Invisible-Pin|pin@7||2.5|0|0|0||
Ngeneric:Invisible-Pin|pin@8||-2.5|0|0|0||
AThicker|net@0||0|FS1800|pin@1||-2.5|0|pin@0||-1.5|0|ART_color()I10
AThicker|net@1||0|FS2136|pin@5||-1.5|-2|pin@4||1.5|0|ART_color()I10
AThicker|net@2||0|FS3263|pin@4||1.5|0|pin@6||-1.5|2|ART_color()I10
AThicker|net@3||0|FS900|pin@6||-1.5|2|pin@5||-1.5|-2|ART_color()I10
Ectl|D5G2;|pin@2||I
Ein|D5G2;|pin@8||I
Eout|D5G2;|pin@7||O
X

# Cell invCTLp{sch}
CinvCTLp;1{sch}|schematic|993433994000|1061329737000||ATTR_X(D5G2;HNPX-14;Y4;)I1|prototype_center()I[0,0]
INMOS;1{ic}|NMOS@0||0|0.5||E|D0G4;|ATTR_Delay(D5G1;NPTX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X
IPMOS;1{ic}|PMOS@0||0|22||E|D0G4;|ATTR_Delay(D5G1;NPTX3.5;Y-2;)I175|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/2.0
IPMOSwk;1{ic}|PMOSwk@0||0|15||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I175|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/2.0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||-13|15|4|2||
NOff-Page|conn@1||-12|8|4|2||
NOff-Page|conn@2||12.5|8|4|2||
NGround|gnd@0||0|-6.5|3|4||
IinvCTLp;1{ic}|invCTLp@0||15|27.75||E|D0G4;|ATTR_X(D5G1.5;NPX1.5;Y2;)I2
NWire_Pin|pin@0||-5|0.5|0.5|0.5||
NWire_Pin|pin@1||0|20.5|0.5|0.5||
NWire_Pin|pin@2||-2.5|22|0.5|0.5||
NWire_Pin|pin@3||-5|22|0.5|0.5||
Ngeneric:Invisible-Pin|pin@4||0|33|0|0|||ART_message(D5G3;)S[invCTLp]
NWire_Pin|pin@5||0|8|0.5|0.5||
NWire_Pin|pin@6||-5|8|0.5|0.5||
NPower|pwr@0||0|28|3|3||
Awire|net@0||0|0|PMOSwk@0|g|-3|15|conn@0|y|-11|15
Awire|net@1||0|2700|pin@5||0|8|PMOSwk@0|d|0|13
Awire|net@2||0|900|PMOS@0|d|0|20|PMOSwk@0|s|0|17
Awire|net@3||0|900|pin@5||0|8|NMOS@0|d|0|2.5
Awire|net@4||0|2700|pin@0||-5|0.5|pin@6||-5|8
Awire|net@5||0|900|NMOS@0|s|0|-1.5|gnd@0||0|-4.5
Awire|net@6||0|1800|pin@0||-5|0.5|NMOS@0|g|-3|0.5
Awire|net@7||0|1800|PMOS@0|g|-3|22|pin@2||-2.5|22
Awire|net@8||0|900|pwr@0||0|28|PMOS@0|s|0|24
Awire|net@9||0|2700|PMOS@0|d|0|20|pin@1||0|20.5
Awire|net@10||0|1800|pin@3||-5|22|pin@2||-2.5|22
Awire|net@11||0|900|pin@3||-5|22|pin@6||-5|8
Awire|net@12||0|1800|pin@5||0|8|conn@2|a|10.5|8|SIM_verilog_wire_type(D5G1;)Strireg
Awire|net@13||0|0|pin@6||-5|8|conn@1|y|-10|8
Ectl|D5G2;X-4;|conn@0|y|I
Ein|D5G2;|conn@1|a|I
Eout|D5G2;|conn@2|y|O
X

# Cell invHT{ic}
CinvHT;1{ic}|artwork|1021415734000|1046885287000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOpened-Thicker-Polygon|art@1||-0.25|0|0.5|1|||ART_color()I10|trace()V[-0.25/-0.5,-0.25/0.5,-0.25/0,0.25/0,0.25/0.5,0.25/-0.5]
NThick-Circle|art@2||2|0|1|1|||ART_color()I10
NPin|pin@0||1.5|0|1|1||W
NPin|pin@1||-1.5|0|1|1||W
NPin|pin@2||-2.5|0|0|0||W
NPin|pin@3||-1.5|2|1|1||W
NPin|pin@4||-1.5|-2|1|1||W
Nschematic:Bus_Pin|pin@5||-2.5|0|0|0||
Nschematic:Bus_Pin|pin@6||2.5|0|0|0||
AThicker|net@0||0|FS0|pin@1||-1.5|0|pin@2||-2.5|0|ART_color()I10
AThicker|net@1||0|FS2700|pin@4||-1.5|-2|pin@3||-1.5|2|ART_color()I10
AThicker|net@2||0|FS336|pin@0||1.5|0|pin@4||-1.5|-2|ART_color()I10
AThicker|net@3||0|FS3263|pin@0||1.5|0|pin@3||-1.5|2|ART_color()I10
Ein|D5G1;|pin@5||I
Eout|D5G1;|pin@6||O
X

# Cell invHT{sch}
CinvHT;1{sch}|schematic|1021415734000|1084347213000||ATTR_Delay(D5G1;HNPX-12;Y-5.5;)I100|ATTR_X(D5G1;HNPX-12;Y-4.5;)I1|ATTR_drive0(D5G1;HNPTX-12;Y-6.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-12;Y-7.5;)Sstrong1|ATTR_verilog_template(D5G1;NTX25.5;Y-15;)Snot ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(in));|prototype_center()I[0,0]
INMOS;1{ic}|NMOS@0||0|-6||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IPMOS;1{ic}|PMOS@0||0|6||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*2.0|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||-11|0|4|2||
NOff-Page|conn@1||8|0|4|2||