redgeneric180.jelib

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

Nschematic:Bus_Pin|pin@5||2.5|0|0|0||
NPin|pin@6||-2.5|1|0|0||W
NPin|pin@7||-1.5|1|1|1||W
Nschematic:Bus_Pin|pin@8||-2.5|1|0|0||
NPin|pin@9||1.5|0|1|1||W
AThicker|net@0||0|FS0|pin@0||-1.5|-1|pin@1||-2.5|-1|ART_color()I10
AThicker|net@1||0|FS2700|pin@3||-1.5|-2|pin@4||-1.5|2|ART_color()I10
AThicker|net@2||0|FS0|pin@7||-1.5|1|pin@6||-2.5|1|ART_color()I10
AThicker|net@3||0|FS336|pin@9||1.5|0|pin@3||-1.5|-2|ART_color()I10
AThicker|net@4||0|FS3263|pin@9||1.5|0|pin@4||-1.5|2|ART_color()I10
Ein[n]|D5G1;|pin@2||I
Ein[p]|D5G1;|pin@8||I
Eout|D5G1;|pin@5||O
X

# Cell inv2i{sch}
Cinv2i;1{sch}|schematic|1021415734000|1117668146407||ATTR_Delay(D5G1;HNPX-13.25;Y-11.25;)I100|ATTR_X(D5G1;HNPX-13.25;Y-10.25;)I1|ATTR_drive0(D5G1;HNPTX-13.25;Y-12.25;)Sstrong0|ATTR_drive1(D5G1;HNPTX-13.25;Y-13.25;)Sstrong1|prototype_center()I[0,0]
INMOS;1{ic}|NMOS@0||0|-5||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IPMOS;1{ic}|PMOS@0||0|6||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||-11|-5|4|2||
NOff-Page|conn@1||-11|6|4|2||
NOff-Page|conn@2||19|0|4|2||
NGround|gnd@0||0|-12|3|4||
Iinv2i;1{ic}|inv2i@0||25|13||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(PT)Sstrong0|ATTR_drive1(PT)Sstrong1
Ngeneric:Invisible-Pin|pin@0||0.5|22|0|0|||ART_message(D5G6;)S[inv2i]
Ngeneric:Invisible-Pin|pin@1||0|18.5|0|0|||ART_message(D5G2;)S[two-input inverter]
Ngeneric:Invisible-Pin|pin@2||28.5|-6|0|0|||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
Ngeneric:Invisible-Pin|pin@3||0|16.5|0|0|||ART_message(D5G2;)S[P to N width ratio is 2 to 1]
NWire_Pin|pin@4||0|0|0.5|0.5||
NPower|pwr@0||0|11.5|3|3||
Awire|net@0||0|0|PMOS@0|g|-3|6|conn@1|y|-9|6
Awire|net@1||0|1800|conn@0|y|-9|-5|NMOS@0|g|-3|-5
Awire|net@2||0|1800|pin@4||0|0|conn@2|a|17|0
Awire|net@3||0|900|pwr@0||0|11.5|PMOS@0|s|0|8
Awire|net@4||0|2700|pin@4||0|0|PMOS@0|d|0|4
Awire|net@5||0|2700|gnd@0||0|-10|NMOS@0|s|0|-7
Awire|net@6||0|900|pin@4||0|0|NMOS@0|d|0|-3
Ein[n]|D5G2;|conn@0|a|I
Ein[p]|D5G2;|conn@1|a|I
Eout|D5G2;|conn@2|y|O
X

# Cell inv2iCTLn{ic}
Cinv2iCTLn;1{ic}|artwork|993434516000|1061318873000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-2|1|1|1|||ART_color()I10
NThick-Circle|art@2||2|0|1|1|||ART_color()I10
Ngeneric:Invisible-Pin|pin@0||-2.5|1|0|0||
NPin|pin@1||-1.5|-1|1|1|R|W
NPin|pin@2||-2.5|-1|1|1|R|W
Ngeneric:Invisible-Pin|pin@3||0|-2|0|0||
Ngeneric:Invisible-Pin|pin@4||0|0|0|0|||ART_message(D5G1.5;)S[CTLn]
NPin|pin@5||1.5|0|0.5|0.5||W
NPin|pin@6||-1.5|-2|0.5|0.5||W
NPin|pin@7||-1.5|2|0.5|0.5||W
Ngeneric:Invisible-Pin|pin@8||2.5|0|0|0||
Ngeneric:Invisible-Pin|pin@9||-2.5|-1|0|0||
NPin|pin@10||0|-2|1|1|RR|W
NPin|pin@11||0|-1|1|1|RR|W
AThicker|net@0||0|FS1800|pin@2||-2.5|-1|pin@1||-1.5|-1|ART_color()I10
AThicker|net@1||0|FS2136|pin@6||-1.5|-2|pin@5||1.5|0|ART_color()I10
AThicker|net@2||0|FS3263|pin@5||1.5|0|pin@7||-1.5|2|ART_color()I10
AThicker|net@3||0|FS900|pin@7||-1.5|2|pin@6||-1.5|-2|ART_color()I10
AThicker|net@4||0|FS2700|pin@10||0|-2|pin@11||0|-1|ART_color()I10
Ectl|D5G2;|pin@3||I
EinN|D5G2;|pin@9||I
EinP|D5G2;|pin@0||I
Eout|D5G2;|pin@8||O
X

# Cell inv2iCTLn{sch}
Cinv2iCTLn;1{sch}|schematic|993433994000|1061329731000||ATTR_X(D5G2;HNPX-19;Y-5;)I1|prototype_center()I[0,0]
INMOS;1{ic}|NMOS@0||0|0.5||E|D0G4;|ATTR_Delay(D5G1;NPTX3.5;Y-2;)I175|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*2.0
INMOSwk;1{ic}|NMOSwk@0||0|9||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I175|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*2.0
IPMOS;1{ic}|PMOS@0||0|22||E|D0G4;|ATTR_Delay(D5G1;NPTX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/2.0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||-11|22|4|2||
NOff-Page|conn@1||-12|9|4|2||
NOff-Page|conn@2||-12|0.5|4|2||
NOff-Page|conn@3||12.5|16|4|2||
NGround|gnd@0||0|-6.5|3|4||
Iinv2iCTLn;1{ic}|inv2iCTL@0||15|27.75||E|D0G4;|ATTR_X(D5G1.5;NPX1.5;Y2;)I2
NWire_Pin|pin@0||0|20.5|0.5|0.5||
NWire_Pin|pin@1||-2.5|22|0.5|0.5||
Ngeneric:Invisible-Pin|pin@2||0|33|0|0|||ART_message(D5G3;)S[inv2iCTLn]
NWire_Pin|pin@3||0|16|0.5|0.5||
NPower|pwr@0||0|28|3|3||
Awire|net@0||0|0|PMOS@0|g|-3|22|conn@0|y|-9|22
Awire|net@1||0|0|NMOS@0|g|-3|0.5|conn@2|y|-10|0.5
Awire|net@2||0|900|NMOS@0|s|0|-1.5|gnd@0||0|-4.5
Awire|net@3||0|1800|PMOS@0|g|-3|22|pin@1||-2.5|22
Awire|net@4||0|900|pwr@0||0|28|PMOS@0|s|0|24
Awire|net@5||0|2700|PMOS@0|d|0|20|pin@0||0|20.5
Awire|net@6||0|1800|pin@3||0|16|conn@3|a|10.5|16|SIM_verilog_wire_type(D5G1;)Strireg
Awire|net@7||0|2700|NMOS@0|d|0|2.5|NMOSwk@0|s|0|7
Awire|net@8||0|900|pin@3||0|16|NMOSwk@0|d|0|11
Awire|net@9||0|900|PMOS@0|d|0|20|pin@3||0|16
Awire|net@10||0|0|NMOSwk@0|g|-3|9|conn@1|y|-10|9
Ectl|D5G2;X-4;|conn@1|y|I
EinN|D5G2;|conn@2|a|I
EinP|D4G2;|conn@0|a|I
Eout|D5G2;|conn@3|y|O
X

# Cell inv2iCTLp{ic}
Cinv2iCTLp;1{ic}|artwork|993434516000|1061318158000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||2|0|1|1|||ART_color()I10
NThick-Circle|art@2||0|-1.5|1|1|||ART_color()I10
NThick-Circle|art@3||-2|1|1|1|||ART_color()I10
Ngeneric:Invisible-Pin|pin@0||-2.5|-1|0|0||
Ngeneric:Invisible-Pin|pin@1||2.5|0|0|0||
NPin|pin@2||-1.5|2|0.5|0.5||W
NPin|pin@3||-1.5|-2|0.5|0.5||W
NPin|pin@4||1.5|0|0.5|0.5||W
Ngeneric:Invisible-Pin|pin@5||0|0|0|0|||ART_message(D5G1.5;)S[CTLp]
Ngeneric:Invisible-Pin|pin@6||0|-2|0|0||
NPin|pin@7||-2.5|-1|1|1|R|W
NPin|pin@8||-1.5|-1|1|1|R|W
Ngeneric:Invisible-Pin|pin@9||-2.5|1|0|0||
AThicker|net@0||0|FS900|pin@2||-1.5|2|pin@3||-1.5|-2|ART_color()I10
AThicker|net@1||0|FS3263|pin@4||1.5|0|pin@2||-1.5|2|ART_color()I10
AThicker|net@2||0|FS2136|pin@3||-1.5|-2|pin@4||1.5|0|ART_color()I10
AThicker|net@3||0|FS1800|pin@7||-2.5|-1|pin@8||-1.5|-1|ART_color()I10
Ectl|D5G2;|pin@6||I
EinN|D5G2;|pin@0||I
EinP|D5G2;|pin@9||I
Eout|D5G2;|pin@1||O
X

# Cell inv2iCTLp{sch}
Cinv2iCTLp;1{sch}|schematic|993433994000|1061329733000||ATTR_X(D5G2;HNPX-19;Y-5;)I1|prototype_center()I[0,0]
INMOS;1{ic}|NMOS@0||0|0.5||E|D0G4;|ATTR_Delay(D5G1;NPTX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X
IPMOS;1{ic}|PMOS@0||0|22||E|D0G4;|ATTR_Delay(D5G1;NPTX3.5;Y-2;)I175|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/2.0
IPMOSwk;1{ic}|PMOSwk@0||0|15||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I175|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/2.0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||12.5|8|4|2||
NOff-Page|conn@1||-12|0.5|4|2||
NOff-Page|conn@2||-11|15|4|2||
NOff-Page|conn@3||-11|22|4|2||
NGround|gnd@0||0|-6.5|3|4||
Iinv2iCTLp;1{ic}|inv2iCTL@0||15|27.75||E|D0G4;|ATTR_X(D5G1.5;NPX1.5;Y2;)I2
NWire_Pin|pin@0||0|8|0.5|0.5||
Ngeneric:Invisible-Pin|pin@1||0|33|0|0|||ART_message(D5G3;)S[inv2iCTLp]
NWire_Pin|pin@2||-2.5|22|0.5|0.5||
NWire_Pin|pin@3||0|20.5|0.5|0.5||
NPower|pwr@0||0|28|3|3||
Awire|net@0||0|1800|pin@0||0|8|conn@0|a|10.5|8|SIM_verilog_wire_type(D5G1;)Strireg
Awire|net@1||0|2700|PMOS@0|d|0|20|pin@3||0|20.5
Awire|net@2||0|900|pwr@0||0|28|PMOS@0|s|0|24
Awire|net@3||0|1800|PMOS@0|g|-3|22|pin@2||-2.5|22
Awire|net@4||0|900|NMOS@0|s|0|-1.5|gnd@0||0|-4.5
Awire|net@5||0|900|pin@0||0|8|NMOS@0|d|0|2.5
Awire|net@6||0|900|PMOS@0|d|0|20|PMOSwk@0|s|0|17
Awire|net@7||0|2700|pin@0||0|8|PMOSwk@0|d|0|13
Awire|net@8||0|0|PMOSwk@0|g|-3|15|conn@2|y|-9|15
Awire|net@9||0|0|NMOS@0|g|-3|0.5|conn@1|y|-10|0.5
Awire|net@10||0|0|PMOS@0|g|-3|22|conn@3|y|-9|22
Ectl|D5G2;X-4;|conn@2|y|I
EinN|D5G2;|conn@1|a|I
EinP|D4G2;|conn@3|a|I
Eout|D5G2;|conn@0|y|O
X

# Cell inv2iHT{ic}
Cinv2iHT;1{ic}|artwork|1021415734000|1084382443000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-1|1|1|1|||ART_color()I10
NThick-Circle|art@2||2|0|1|1|||ART_color()I10
NOpened-Thicker-Polygon|art@3||-0.25|0|0.5|1|||ART_color()I10|trace()V[-0.25/-0.5,-0.25/0.5,-0.25/0,0.25/0,0.25/0.5,0.25/-0.5]
NPin|pin@0||-1.5|-1|1|1||W
NPin|pin@1||-2.5|-1|0|0||W
Nschematic:Bus_Pin|pin@2||-2.5|1|2|2||
Nschematic:Bus_Pin|pin@3||-2.5|-1|2|2||
Nschematic:Bus_Pin|pin@4||2.5|0|0|0||
NPin|pin@5||-1.5|-2|1|1||W
NPin|pin@6||-1.5|2|1|1||W
NPin|pin@7||-2.5|1|0|0||W
NPin|pin@8||-1.5|1|1|1||W
NPin|pin@9||1.5|0|1|1||W
AThicker|net@0||0|FS0|pin@0||-1.5|-1|pin@1||-2.5|-1|ART_color()I10
AThicker|net@1||0|FS3263|pin@9||1.5|0|pin@6||-1.5|2|ART_color()I10
AThicker|net@2||0|FS336|pin@9||1.5|0|pin@5||-1.5|-2|ART_color()I10
AThicker|net@3||0|FS2700|pin@5||-1.5|-2|pin@6||-1.5|2|ART_color()I10
AThicker|net@4||0|FS0|pin@8||-1.5|1|pin@7||-2.5|1|ART_color()I10
Ein[n]|D5G1;|pin@3||I
Ein[p]|D5G1;|pin@2||I
Eout|D5G1;|pin@4||O
X

# Cell inv2iHT{sch}
Cinv2iHT;1{sch}|schematic|1021415734000|1117668125989||ATTR_Delay(D5G1;HNPX-14.5;Y-11.5;)I100|ATTR_X(D5G1;HNPX-14.5;Y-10.5;)I1|ATTR_drive0(D5G1;HNPTX-14.5;Y-12.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-14.5;Y-13.5;)Sstrong1|prototype_center()I[0,0]
INMOS;1{ic}|NMOS@0||0|-6||E|D0G4;|ATTR_Delay(D5G1;NOJPTX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IPMOS;1{ic}|PMOS@0||0|6||E|D0G4;|ATTR_Delay(D5G1;NOJPTX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*2.0|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||-11|-6|4|2||
NOff-Page|conn@1||-11.5|6|4|2||
NOff-Page|conn@2||8|0|4|2||
NGround|gnd@0||0|-12.5|3|4||
Iinv2iHT;1{ic}|inv2iHT@0||16|10.5||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(PT)Sstrong0|ATTR_drive1(PT)Sstrong1
Ngeneric:Invisible-Pin|pin@4||-1|24|0|0|||ART_message(D5G6;)S[inv2iHT]
Ngeneric:Invisible-Pin|pin@5||0|19|0|0|||ART_message(D5G2;)S[two-input HI-threshold inverter]
NWire_Pin|pin@6||0|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@7||1|17|0|0|||ART_message(D5G2;)S[P to N width ratio is 4 to 1]
Ngeneric:Invisible-Pin|pin@8||25|-9|0|0|||ART_message(D5G2;)S[X is drive strength,P drive strength is twice N strength]
NPower|pwr@0||0|12.5|3|3||
Awire|net@8||0|900|NMOS@0|s|0|-8|gnd@0||0|-10.5
Awire|net@9||0|900|pin@6||0|0|NMOS@0|d|0|-4
Awire|net@10||0|2700|PMOS@0|s|0|8|pwr@0||0|12.5
Awire|net@11||0|2700|pin@6||0|0|PMOS@0|d|0|4
Awire|net@12||0|0|conn@2|a|6|0|pin@6||0|0
Awire|net@17||0|1800|conn@0|y|-9|-6|NMOS@0|g|-3|-6
Awire|net@18||0|1800|conn@1|y|-9.5|6|PMOS@0|g|-3|6
Ein[n]|D5G2;|conn@0|a|I
Ein[p]|D5G2;|conn@1|a|I
Eout|D5G2;|conn@2|y|O
X

# Cell inv2iLT{ic}
Cinv2iLT;1{ic}|artwork|1021415734000|1048540302000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-1|1|1|1|||ART_color()I10
NOpened-Thicker-Polygon|art@2||-0.25|0|0.5|1|||ART_color()I10|trace()V[-0.25/0.5,-0.25/-0.5,0.25/-0.5]
NThick-Circle|art@3||2|0|1|1|||ART_color()I10
NPin|pin@0||-2.5|-1|0|0||W
NPin|pin@1||-1.5|-1|1|1||W
Nschematic:Bus_Pin|pin@2||-2.5|-1|2|2||
NPin|pin@3||1.5|0|1|1||W
NPin|pin@4||-1.5|1|1|1||W
NPin|pin@5||-2.5|1|0|0||W
NPin|pin@6||-1.5|2|1|1||W
NPin|pin@7||-1.5|-2|1|1||W
Nschematic:Bus_Pin|pin@8||-2.5|1|0|0||
Nschematic:Bus_Pin|pin@9||2.5|0|0|0||
AThicker|net@0||0|FS0|pin@1||-1.5|-1|pin@0||-2.5|-1|ART_color()I10
AThicker|net@1||0|FS0|pin@4||-1.5|1|pin@5||-2.5|1|ART_color()I10
AThicker|net@2||0|FS2700|pin@7||-1.5|-2|pin@6||-1.5|2|ART_color()I10
AThicker|net@3||0|FS336|pin@3||1.5|0|pin@7||-1.5|-2|ART_color()I10
AThicker|net@4||0|FS3263|pin@3||1.5|0|pin@6||-1.5|2|ART_color()I10
Ein[n]|D5G1;|pin@2||I
Ein[p]|D5G1;|pin@8||I
Eout|D5G1;|pin@9||O
X

# Cell inv2iLT{sch}
Cinv2iLT;1{sch}|schematic|1021415734000|1117668141650||ATTR_Delay(D5G1;HNPX-12;Y-13;)I100|ATTR_X(D5G1;HNPX-12;Y-12;)I1|ATTR_drive0(D5G1;HNPTX-12;Y-14;)Sstrong0|ATTR_drive1(D5G1;HNPTX-12;Y-15;)Sstrong1|prototype_center()I[0,0]
INMOS;1{ic}|NMOS@0||0|-6||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*2.0|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IPMOS;1{ic}|PMOS@0||0|6||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||-9.5|-6|4|2||
NOff-Page|conn@1||-10|6|4|2||
NOff-Page|conn@2||8|0|4|2||
NGround|gnd@0||0|-12.5|3|4||
Iinv2iLT;1{ic}|inv2iLT@0||16|10.5||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(PT)Sstrong0|ATTR_drive1(PT)Sstrong1
NWire_Pin|pin@0||-3|-6|0.5|0.5||
NWire_Pin|pin@2||-3|6|0.5|0.5||
Ngeneric:Invisible-Pin|pin@4||25|-10|0|0|||ART_message(D5G2;)S[X is drive strength,N drive strength is twice P strength]
Ngeneric:Invisible-Pin|pin@5||0.5|17|0|0|||ART_message(D5G2;)S[This is a 2 to 2 width ratio inverter]
NWire_Pin|pin@6||0|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@7||0|19|0|0|||ART_message(D5G2;)S[two-input LO-threshold inverter]
Ngeneric:Invisible-Pin|pin@8||-1|24|0|0|||ART_message(D5G6;)S[inv2iLT]
NPower|pwr@0||0|12.5|3|3||
Awire|net@1||0|1800|pin@0||-3|-6|NMOS@0|g|-3|-6
Awire|net@5||0|1800|pin@2||-3|6|PMOS@0|g|-3|6
Awire|net@8||0|900|pwr@0||0|12.5|PMOS@0|s|0|8
Awire|net@9||0|2700|pin@6||0|0|PMOS@0|d|0|4
Awire|net@10||0|2700|gnd@0||0|-10.5|NMOS@0|s|0|-8