redgeneric180.jelib

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

Awire|net@5||0|1800|pin@3||0|11.5|conn@3|a|3|11.5
Ed|D5G2;|conn@1|y|B
Eg|D5G2;|conn@2|a|I
Epower|D4G2;|conn@0|a|I
Es|D5G2;|conn@3|y|B
X

# Cell PMOS4wk{ic}
CPMOS4wk;1{ic}|artwork|1021415734000|1085595597000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-1.5|0|0.5|0.5|RR||ART_color()I10
NPin|pin@0||-0.5|0.25|1|1|YRR|W
NPin|pin@1||-0.75|0.5|1|1|Y|W
NPin|pin@2||-0.5|0.75|1|1|YRR|W
NPin|pin@3||-0.75|0.5|1|1|Y|W
NPin|pin@4||-0.75|0.5|1|1|Y|W
NPin|pin@5||0|0.5|0|0||W
Nschematic:Bus_Pin|pin@6||0|0.5|2|2||
Ngeneric:Invisible-Pin|pin@7||0|2|0|0||
Nschematic:Bus_Pin|pin@8||0|-2|0|0||
Nschematic:Bus_Pin|pin@9||-3|0|0|0||
NPin|pin@10||0|0.75|0|0||W
NPin|pin@11||-0.75|0.75|1|1||W
NPin|pin@12||-0.75|-0.75|1|1||W
NPin|pin@13||0|-0.75|0|0||W
NPin|pin@14||0|-2|0|0||W
NPin|pin@15||-3|0|0|0|RR|W
NPin|pin@16||-1.75|0|1|1|RRR|W
NPin|pin@17||0|2|0|0||W
NPin|pin@18||-1.25|0.75|1|1|Y|W
NPin|pin@19||-1.25|-0.75|1|1|Y|W
Ngeneric:Invisible-Pin|pin@20||-0.5|0|0|0|||ART_message(D5G1;)S[wk]
AThicker|net@0||0|FS3150|pin@0||-0.5|0.25|pin@1||-0.75|0.5|ART_color()I10
AThicker|net@1||0|FS0|pin@5||0|0.5|pin@4||-0.75|0.5|ART_color()I10
AThicker|net@2||0|FS450|pin@2||-0.5|0.75|pin@3||-0.75|0.5|ART_color()I10
AThicker|net@3||0|FS0|pin@10||0|0.75|pin@11||-0.75|0.75|ART_color()I10
AThicker|net@4||0|FS1800|pin@12||-0.75|-0.75|pin@13||0|-0.75|ART_color()I10
AThicker|net@5||0|FS1800|pin@15||-3|0|pin@16||-1.75|0|ART_color()I10
AThicker|net@6||0|FS2700|pin@10||0|0.75|pin@17||0|2|ART_color()I10
AThicker|net@7||0|FS900|pin@13||0|-0.75|pin@14||0|-2|ART_color()I10
AThicker|net@8||0|FS900|pin@11||-0.75|0.75|pin@12||-0.75|-0.75|ART_color()I10
AThicker|net@9||0|FS2700|pin@19||-1.25|-0.75|pin@18||-1.25|0.75|ART_color()I10
Ed|D8G1;|pin@8||B
Eg|D6G1;|pin@9||I
Epower|D5G1;|pin@6||I
Es|D2G1;|pin@7||B
X

# Cell PMOS4wk{sch}
CPMOS4wk;1{sch}|schematic|1021415734000|1098422023000||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_X(D5G1;HNPX-8.5;Y1.25;)I1|prototype_center()I[0,0]
IorangeGeneric180:PMOS4fwk;1{ic}|PMOS4fwk@0||0|7||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5G1;NOJPX3.5;)S@X == 0 ? 0 : @X < 0.25 ? (0.25 * (2 - 0.4) / @X + 0.4) : 2|ATTR_W(D6G1;NOJPX2;Y1;)S@X > 0.25 ? 6.0*@X : 3
IPMOS4wk;1{ic}|PMOS4wk@0||23.25|15.5||E|D0G4;|ATTR_Delay(D5G1;NPTX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||9.5|7.5|4|2|YRR|
NOff-Page|conn@1||5|11.5|4|2||
NOff-Page|conn@2||-8|7|4|2||
NOff-Page|conn@3||5|1|4|2||
NWire_Pin|pin@0||0|11.5|0.5|0.5||
NWire_Pin|pin@1||0|1|0.5|0.5||
Ngeneric:Invisible-Pin|pin@2||-0.5|23.5|0|0|||ART_message(D5G6;)S[PMOS4wk]
Ngeneric:Invisible-Pin|pin@3||-0.5|18.5|0|0|||ART_message(D5G2;)S[4 terminal weak PMOS device]
Awire|net@0||0|1800|PMOS4fwk@0|b|0|7.5|conn@0|y|7.5|7.5
Awire|net@1||0|900|pin@0||0|11.5|PMOS4fwk@0|s|0|9
Awire|net@2||0|1800|conn@2|y|-6|7|PMOS4fwk@0|g|-3|7
Awire|net@3||0|2700|pin@1||0|1|PMOS4fwk@0|d|0|5
Awire|net@4||0|1800|pin@0||0|11.5|conn@1|a|3|11.5
Awire|net@5||0|0|conn@3|a|3|1|pin@1||0|1
Ed|D5G2;|conn@3|y|B
Eg|D5G2;|conn@2|a|I
Epower|D4G2;|conn@0|a|I
Es|D5G2;|conn@1|y|B
X

# Cell PMOSwk{ic}
CPMOSwk;1{ic}|artwork|1021415734000|1047944997000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-1.5|0|0.5|0.5|RR||ART_color()I10
Ngeneric:Invisible-Pin|pin@0||-0.5|0|0|0|||ART_message(D5G1;)S[wk]
NPin|pin@1||-1.25|-0.75|1|1|Y|W
NPin|pin@2||-1.25|0.75|1|1|Y|W
NPin|pin@3||0|2|0|0||W
NPin|pin@4||-1.75|0|1|1|RRR|W
NPin|pin@5||-3|0|0|0|RR|W
NPin|pin@6||0|-2|0|0||W
NPin|pin@7||0|-0.75|0|0||W
NPin|pin@8||-0.75|-0.75|1|1||W
NPin|pin@9||-0.75|0.75|1|1||W
NPin|pin@10||0|0.75|0|0||W
Nschematic:Bus_Pin|pin@11||-3|0|0|0||
Nschematic:Bus_Pin|pin@12||0|-2|0|0||
Ngeneric:Invisible-Pin|pin@13||0|2|0|0||
AThicker|net@0||0|FS2700|pin@1||-1.25|-0.75|pin@2||-1.25|0.75|ART_color()I10
AThicker|net@1||0|FS900|pin@9||-0.75|0.75|pin@8||-0.75|-0.75|ART_color()I10
AThicker|net@2||0|FS900|pin@7||0|-0.75|pin@6||0|-2|ART_color()I10
AThicker|net@3||0|FS2700|pin@10||0|0.75|pin@3||0|2|ART_color()I10
AThicker|net@4||0|FS1800|pin@5||-3|0|pin@4||-1.75|0|ART_color()I10
AThicker|net@5||0|FS1800|pin@8||-0.75|-0.75|pin@7||0|-0.75|ART_color()I10
AThicker|net@6||0|FS0|pin@10||0|0.75|pin@9||-0.75|0.75|ART_color()I10
Ed|D8G1;|pin@12||B
Eg|D6G1;|pin@11||I
Es|D2G1;|pin@13||B
X

# Cell PMOSwk{sch}
CPMOSwk;1{sch}|schematic|1021415734000|1098423771000||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_X(D5G1;HNPX-8.5;Y1.25;)I1|ATTR_drain_shared(D5G1;HNPX-8.5;Y-2;)I0|ATTR_source_shared(D5G1;HNPX-8.5;Y-4;)I0|prototype_center()I[0,0]
IorangeGeneric180:PMOSfwk;1{ic}|PMOSfwk@0||0|7||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5G1;NOJPX3.5;)S@X == 0 ? 0 : @X < 0.5 ? (0.5 * (2 - 0.4) / @X + 0.4) : 2|ATTR_W(D6G1;NOJPX2;Y1;)S@X > 0.5 ? 6.0*@X : 3|ATTR_drain_shared(D5G1;OJPX0.5;Y-2.5;)S@drain_shared|ATTR_source_shared(D5G1;OJPX0.5;Y2.5;)S@source_shared
IPMOSwk;1{ic}|PMOSwk@0||23.25|16||E|D0G4;|ATTR_Delay(D5G1;NPTX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||5|1|4|2||
NOff-Page|conn@1||-8|7|4|2||
NOff-Page|conn@2||5|11.5|4|2||
Ngeneric:Invisible-Pin|pin@0||-0.5|18.5|0|0|||ART_message(D5G2;)S[3 terminal weak PMOS device]
Ngeneric:Invisible-Pin|pin@1||-0.5|23.5|0|0|||ART_message(D5G6;)S[PMOSwk]
NWire_Pin|pin@2||0|1|0.5|0.5||
NWire_Pin|pin@3||0|11.5|0.5|0.5||
Awire|net@0||0|900|pin@3||0|11.5|PMOSfwk@0|s|0|9
Awire|net@1||0|1800|conn@1|y|-6|7|PMOSfwk@0|g|-3|7
Awire|net@2||0|2700|pin@2||0|1|PMOSfwk@0|d|0|5
Awire|net@3||0|0|conn@0|a|3|1|pin@2||0|1
Awire|net@4||0|1800|pin@3||0|11.5|conn@2|a|3|11.5
Ed|D5G2;|conn@0|y|B
Eg|D5G2;|conn@1|a|I
Es|D5G2;|conn@2|y|B
X

# Cell hifidely{ic}
Chifidely;1{ic}|artwork|1046374423000|1046374607000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||3.5|0|2|2|RRR||ART_color()I10|ART_degrees()F[0.0,3.1415927]
NPin|pin@0||2|1|1|1||W
NPin|pin@1||2|-1|1|1||W
NPin|pin@2||3|-1|1|1||W
NPin|pin@3||3|1|1|1||W
NPin|pin@4||3.5|-1|1|1||W
NPin|pin@5||-4|-1|1|1||W
NPin|pin@6||-4|1|1|1||W
NPin|pin@7||3.5|1|1|1||W
Nschematic:Bus_Pin|pin@8||4.5|0|2|2||
Nschematic:Bus_Pin|pin@9||-4|0|2|2||
AThicker|net@0||0|FS2700|pin@1||2|-1|pin@0||2|1|ART_color()I10
AThicker|net@1||0|FS2700|pin@2||3|-1|pin@3||3|1|ART_color()I10
AThicker|net@2||0|FS0|pin@4||3.5|-1|pin@5||-4|-1|ART_color()I10
AThicker|net@3||0|FS2700|pin@5||-4|-1|pin@6||-4|1|ART_color()I10
AThicker|net@4||0|FS1800|pin@6||-4|1|pin@7||3.5|1|ART_color()I10
Ein|D5G2;|pin@9||I
Eout|D5G2;|pin@8||O
X

# Cell hifidely{sch}
Chifidely;1{sch}|schematic|1046374013000|1117667893107||prototype_center()I[0,0]
Ispiceparts:Transmission;1{ic}|Transmis@0||-8|-1||E|D0G4;|ATTR_Delay(D5G0.5;NPY-1;)S500ps|ATTR_z0(D5G0.5;NPY1;)I50
Ispiceparts:VCVS;1{ic}|VCVS@0||11|-1||E|D0G4;|ATTR_Gain(D5G0.5;NPY1;)I1|ATTR_Maximum(D5G0.5;NPY-1;)S10V|ATTR_Minimum(D5G0.5;NP)S-10V
Ispiceparts:VCVS;1{ic}|VCVS@1||-21|-1||E|D0G4;|ATTR_Gain(D5G0.5;NPY1;)I1|ATTR_Maximum(D5G0.5;NPY-1;)S10V|ATTR_Minimum(D5G0.5;NP)S-10V
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||20|1|4|2||
NOff-Page|conn@1||-35.5|3|4|2||
NGround|gnd@0||20|-9|3|4||
NGround|gnd@1||-31.5|-9|3|4||
NGround|gnd@2||1.5|-9|3|4||
NGround|gnd@3||-14|-9|3|4||
Ihifidely;1{ic}|hifidely@0||16.5|13.5||E|D0G4;
NWire_Pin|pin@0||-28|1|0.5|0.5||
NWire_Pin|pin@1||-28|3|0.5|0.5||
NWire_Pin|pin@3||-31.5|3|0.5|0.5||
NWire_Pin|pin@5||20|-3|0.5|0.5||
NWire_Pin|pin@6||1.5|2.75|0.5|0.5||
NWire_Pin|pin@8||4|2.75|0.5|0.5||
NWire_Pin|pin@9||-1|2.75|0.5|0.5||
NWire_Pin|pin@24||-31.5|-3|0.5|0.5||
NWire_Pin|pin@25||-14|-3|0.5|0.5||
NWire_Pin|pin@26||4|1|0.5|0.5||
NWire_Pin|pin@27||-1|1|0.5|0.5||
NWire_Pin|pin@28||1.5|-3|0.5|0.5||
Ngeneric:Invisible-Pin|pin@29||-12|17|0|0|||ART_message(D5G5;)Shifidelay
Ngeneric:Invisible-Pin|pin@30||-13|11.5|0|0|||ART_message(D5G2;)Sideal delay for spice simulation
NResistor|res@0||-31.5|0|6|1|R||SCHEM_resistance(D5G1;)I1000000
NResistor|res@1||1.5|0|6|1|R||SCHEM_resistance(D5G1;)I50
Awire|net@1||0|2700|pin@0||-28|1|pin@1||-28|3
Awire|net@2||0|0|pin@1||-28|3|pin@3||-31.5|3
Awire|net@5||0|0|pin@3||-31.5|3|conn@1|y|-33.5|3
Awire|net@11||0|900|pin@5||20|-3|gnd@0||20|-7
Awire|net@13||0|900|pin@6||1.5|2.75|res@1|b|1.5|2
Awire|net@14||0|0|pin@8||4|2.75|pin@6||1.5|2.75
Awire|net@15||0|0|pin@6||1.5|2.75|pin@9||-1|2.75
Awire|net@24||0|0|Transmis@0|a|-13|1|VCVS@1|x|-16|1
Awire|net@25||0|1800|VCVS@1|y|-16|-3|pin@25||-14|-3
Awire|net@26||0|1800|pin@28||1.5|-3|VCVS@0|b|6|-3
Awire|net@28||0|0|conn@0|a|18|1|VCVS@0|x|16|1
Awire|net@29||0|0|pin@5||20|-3|VCVS@0|y|16|-3
Awire|net@30||0|1800|pin@0||-28|1|VCVS@1|a|-26|1
Awire|net@31||0|2700|res@0|b|-31.5|2|pin@3||-31.5|3
Awire|net@32||0|2700|gnd@1||-31.5|-7|pin@24||-31.5|-3
Awire|net@33||0|900|pin@28||1.5|-3|gnd@2||1.5|-7
Awire|net@34||0|2700|pin@24||-31.5|-3|res@0|a|-31.5|-2
Awire|net@35||0|0|VCVS@1|b|-26|-3|pin@24||-31.5|-3
Awire|net@36||0|1800|pin@25||-14|-3|Transmis@0|b|-13|-3
Awire|net@38||0|900|pin@8||4|2.75|pin@26||4|1
Awire|net@39||0|1800|pin@26||4|1|VCVS@0|a|6|1
Awire|net@40||0|900|pin@9||-1|2.75|pin@27||-1|1
Awire|net@41||0|0|pin@27||-1|1|Transmis@0|x|-3|1
Awire|net@42||0|900|res@1|a|1.5|-2|pin@28||1.5|-3
Awire|net@43||0|1800|Transmis@0|y|-3|-3|pin@28||1.5|-3
Awire|net@44||0|2700|gnd@3||-14|-7|pin@25||-14|-3
Ein|D5G2;|conn@1|y|I
Eout|D5G2;|conn@0|y|O
X

# Cell inv{ic}
Cinv;1{ic}|artwork|1021415734000|1044914909000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||2|0|1|1|||ART_color()I10
NPin|pin@0||1.5|0|1|1||W
Nschematic:Bus_Pin|pin@1||-2.5|0|0|0||
NPin|pin@2||-1.5|0|1|1||W
NPin|pin@3||-2.5|0|0|0||W
Nschematic:Bus_Pin|pin@4||2.5|0|0|0||
NPin|pin@5||-1.5|2|1|1||W
NPin|pin@6||-1.5|-2|1|1||W
AThicker|net@0||0|FS3263|pin@0||1.5|0|pin@5||-1.5|2|ART_color()I10
AThicker|net@1||0|FS336|pin@0||1.5|0|pin@6||-1.5|-2|ART_color()I10
AThicker|net@2||0|FS0|pin@2||-1.5|0|pin@3||-2.5|0|ART_color()I10
AThicker|net@3||0|FS2700|pin@6||-1.5|-2|pin@5||-1.5|2|ART_color()I10
Ein|D5G1;|pin@1||I
Eout|D5G1;|pin@4||O
X

# Cell inv{sch}
Cinv;1{sch}|schematic|1021415734000|1060030088000||ATTR_Delay(D5G1;HNPX-12;Y-5;)I100|ATTR_X(D5G1;HNPX-12;Y-4;)I1|ATTR_drive0(D5G1;HNPTX-12;Y-6;)Sstrong0|ATTR_drive1(D5G1;HNPTX-12;Y-7;)Sstrong1|ATTR_verilog_template(D5G1;NTX24.5;Y-11;)Snot ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(in));|prototype_center()I[0,0]
INMOS;1{ic}|NMOS@0||0|-5||E|D0G4;|ATTR_Delay(D5G1;NOJPTX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IPMOS;1{ic}|PMOS@0||0|6||E|D0G4;|ATTR_Delay(D5G1;NOJPTX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||19|0|4|2||
NOff-Page|conn@1||-17.5|0|4|2||
NGround|gnd@0||0|-12|3|4||
Iinv;1{ic}|inv@0||25|13||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(PT)Sstrong0|ATTR_drive1(PT)Sstrong1
NWire_Pin|pin@0||-4|0|0.5|0.5||
NWire_Pin|pin@1||0|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@2||0|16.5|0|0|||ART_message(D5G2;)S[P to N width ratio is 2 to 1]
Ngeneric:Invisible-Pin|pin@3||28.5|-6|0|0|||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
Ngeneric:Invisible-Pin|pin@4||0|18.5|0|0|||ART_message(D5G2;)S[one-parameter fixed size (non-LE) inverter]
Ngeneric:Invisible-Pin|pin@5||0.5|22|0|0|||ART_message(D5G6;)S[inv]
NWire_Pin|pin@6||-4|6|0.5|0.5||
NWire_Pin|pin@7||-4|-5|0.5|0.5||
NPower|pwr@0||0|11.5|3|3||
Awire|net@0||0|0|conn@0|a|17|0|pin@1||0|0
Awire|net@1||0|0|pin@0||-4|0|conn@1|y|-15.5|0
Awire|net@2||0|900|pin@6||-4|6|pin@0||-4|0
Awire|net@3||0|900|pin@0||-4|0|pin@7||-4|-5
Awire|net@4||0|2700|gnd@0||0|-10|NMOS@0|s|0|-7
Awire|net@5||0|2700|NMOS@0|d|0|-3|pin@1||0|0
Awire|net@6||0|0|NMOS@0|g|-3|-5|pin@7||-4|-5
Awire|net@7||0|2700|PMOS@0|s|0|8|pwr@0||0|11.5
Awire|net@8||0|0|PMOS@0|g|-3|6|pin@6||-4|6
Awire|net@9||0|2700|pin@1||0|0|PMOS@0|d|0|4
Ein|D5G2;|conn@1|a|I
Eout|D5G2;|conn@0|y|O
X

# Cell inv2i{ic}
Cinv2i;1{ic}|artwork|1021415734000|1048534752000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-1|1|1|1|||ART_color()I10
NThick-Circle|art@2||2|0|1|1|||ART_color()I10
NPin|pin@0||-1.5|-1|1|1||W
NPin|pin@1||-2.5|-1|0|0||W
Nschematic:Bus_Pin|pin@2||-2.5|-1|2|2||
NPin|pin@3||-1.5|-2|1|1||W
NPin|pin@4||-1.5|2|1|1||W