redgeneric180.jelib

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

# header information:
HredGeneric180|8.02o|USER_electrical_units()I70464

# Views:
Vicon|ic
Vschematic|sch

# External Libraries and cells:

LorangeGeneric180|orangeGeneric180
RNMOSf;1{ic}|-3|0|-2|2|1021415734000|1046884569000
Fd|0|2
Fg|-3|0
Fs|0|-2
RNMOSfwk;1{ic}|-3|0|-2|2|1021415734000|1047945058000
Fd|0|2
Fg|-3|0
Fs|0|-2
RPMOS4f;1{ic}|-3|0|-2|2|1021415734000|1085594334000
Fb|0|0.5
Fd|0|-2
Fg|-3|0
Fs|0|2
RPMOS4fwk;1{ic}|-3|0|-2|2|1021415734000|1098422023000
Fb|0|0.5
Fd|0|-2
Fg|-3|0
Fs|0|2
RPMOSf;1{ic}|-3|0|-2|2|1021415734000|1046821723000
Fd|0|-2
Fg|-3|0
Fs|0|2
RPMOSfwk;1{ic}|-3|0|-2|2|1021415734000|1047945019000
Fd|0|-2
Fg|-3|0
Fs|0|2
Rwire180;1{ic}|-3|3|-1.25|1.25|1083966364000|1084405602000
Fa|-2.5|0
Fb|2.5|0

Lspiceparts|jar:file:/home/cad/electric/8.00lcl/electric.jar!/com/sun/electric/lib/spiceparts.jelib
RTransmission;1{ic}|-5|5|-3|3|1006816118000|1103661364546
Fa|-5|2
Fb|-5|-2
Fx|5|2
Fy|5|-2
RVCVS;1{ic}|-5|5|-3|3|1006816118000|1103661387937
Fa|-5|2
Fb|-5|-2
Fx|5|2
Fy|5|-2

# Technologies:
Tartwork
Tgeneric
Tmocmos
Tschematic

# Cell NMOS{ic}
CNMOS;1{ic}|artwork|1021415734000|1045501743000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0|R|AV
Ngeneric:Invisible-Pin|pin@0||0|-2|0|0||
NPin|pin@1||-1.5|0|1|1|RR|W
NPin|pin@2||-3|0|0|0|RR|W
Nschematic:Bus_Pin|pin@3||-3|0|0|0||
Nschematic:Bus_Pin|pin@4||0|2|0|0||
NPin|pin@5||0|-2|0|0||W
NPin|pin@6||-1.5|1|1|1||W
NPin|pin@7||-1.5|-1|1|1||W
NPin|pin@8||0|-1|0|0||W
NPin|pin@9||-0.75|-1|1|1||W
NPin|pin@10||-0.75|1|1|1||W
NPin|pin@11||0|1|0|0||W
NPin|pin@12||0|2|0|0||W
AThicker|net@0||0|FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I10
AThicker|net@1||0|FS1800|pin@2||-3|0|pin@1||-1.5|0|ART_color()I10
AThicker|net@2||0|FS900|pin@6||-1.5|1|pin@7||-1.5|-1|ART_color()I10
AThicker|net@3||0|FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I10
AThicker|net@4||0|FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I10
AThicker|net@5||0|FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I10
AThicker|net@6||0|FS900|pin@12||0|2|pin@11||0|1|ART_color()I10
Ed|D5G1;|pin@4||B
Eg|D5G1;|pin@3||I
Es|D5G1;|pin@0||B
X

# Cell NMOS{sch}
CNMOS;1{sch}|schematic|1021415734000|1098400094000||ATTR_Delay(D5G1;HNPX-8.5;Y-12.75;)I100|ATTR_X(D5G1;HNPX-8.5;Y-11.25;)I1|ATTR_drain_shared(D5G1;HNPX-8.5;Y-14.25;)I0|ATTR_source_shared(D5G1;HNPX-8.5;Y-15.75;)I0|prototype_center()I[0,0]
INMOS;1{ic}|NMOS@0||24|3||E|D0G4;|ATTR_Delay(D5G1;NPTX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IorangeGeneric180:NMOSf;1{ic}|NMOSf@0||0|-8||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5G1;NOJPX3.5;)S@X == 0 ? 0 : (@X<1) ? (1.0 * (2-0.4) / @X + 0.4) : 2|ATTR_W(D6G1;NOJPX2;Y1;)S@X > 1 ? 3.0*@X : 3|ATTR_drain_shared(D5G1;OJPX0.5;Y2.5;)S@drain_shared|ATTR_source_shared(D5G1;OJPX0.5;Y-2.5;)S@source_shared
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||6|-16.5|4|2||
NOff-Page|conn@1||5.5|0|4|2||
NOff-Page|conn@2||-18.5|-8|4|2||
Ngeneric:Invisible-Pin|pin@0||-13|-2|0|0|||ART_message(D5G1;)S[Note: Gate Resistor removed for,NCC in miniheater chip]
NWire_Pin|pin@1||0|-16.5|0.5|0.5||
NWire_Pin|pin@2||0|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@3||0|8.5|0|0|||ART_message(D5G6;)S[NMOS]
Ngeneric:Invisible-Pin|pin@4||-8.5|-4.5|0|0|||ART_message(D5G1;)S[model,gate,resistance]
Awire|net@0||0|0|NMOSf@0|g|-3|-8|conn@2|y|-16.5|-8
Awire|net@1||0|2700|pin@1||0|-16.5|NMOSf@0|s|0|-10
Awire|net@2||0|900|pin@2||0|0|NMOSf@0|d|0|-6
Awire|net@3||0|1800|pin@1||0|-16.5|conn@0|a|4|-16.5
Awire|net@4||0|1800|pin@2||0|0|conn@1|a|3.5|0
Ed|D5G2;|conn@1|y|B
Eg|D5G2;|conn@2|a|I
Es|D5G2;|conn@0|y|B
X

# Cell NMOSwk{ic}
CNMOSwk;1{ic}|artwork|1021415734000|1047945040000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0|R|AV
Ngeneric:Invisible-Pin|pin@0||-0.5|0|0|0|||ART_message(D5G1;)S[wk]
Ngeneric:Invisible-Pin|pin@1||0|-2|0|0||
NPin|pin@2||-1.25|0|1|1|RR|W
NPin|pin@3||-3|0|0|0|RR|W
Nschematic:Bus_Pin|pin@4||-3|0|0|0||
Nschematic:Bus_Pin|pin@5||0|2|0|0||
NPin|pin@6||0|-2|0|0||W
NPin|pin@7||-1.25|0.75|1|1||W
NPin|pin@8||-1.25|-0.75|1|1||W
NPin|pin@9||0|-0.75|0|0||W
NPin|pin@10||-0.75|-0.75|1|1||W
NPin|pin@11||-0.75|0.75|1|1||W
NPin|pin@12||0|0.75|0|0||W
NPin|pin@13||0|2|0|0||W
AThicker|net@0||0|FS900|pin@11||-0.75|0.75|pin@10||-0.75|-0.75|ART_color()I10
AThicker|net@1||0|FS1800|pin@3||-3|0|pin@2||-1.25|0|ART_color()I10
AThicker|net@2||0|FS900|pin@7||-1.25|0.75|pin@8||-1.25|-0.75|ART_color()I10
AThicker|net@3||0|FS900|pin@9||0|-0.75|pin@6||0|-2|ART_color()I10
AThicker|net@4||0|FS1800|pin@10||-0.75|-0.75|pin@9||0|-0.75|ART_color()I10
AThicker|net@5||0|FS0|pin@12||0|0.75|pin@11||-0.75|0.75|ART_color()I10
AThicker|net@6||0|FS900|pin@13||0|2|pin@12||0|0.75|ART_color()I10
Ed|D5G1;|pin@5||B
Eg|D5G1;|pin@4||I
Es|D5G1;|pin@1||B
X

# Cell NMOSwk{sch}
CNMOSwk;1{sch}|schematic|1021415734000|1052765924000||ATTR_Delay(D5G1;HNPX-8.5;Y-13.25;)I100|ATTR_X(D5G1;HNPX-8.5;Y-12.25;)I1|ATTR_drain_shared(D5G1;HNPX-8.5;Y-14.75;)I0|ATTR_source_shared(D5G1;HNPX-8.5;Y-16.25;)I0|prototype_center()I[0,0]
IorangeGeneric180:NMOSfwk;1{ic}|NMOSfwk@0||0|-8||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5G1;NOJPX3.5;)S@X==0 ? 0 : (@X<1) ? (1*(2-0.4)/@X + 0.4) : 2|ATTR_W(D6G1;NOJPX2;Y1;)S@X>1 ? 3.0*@X : 3|ATTR_drain_shared(D5G1;OJPX0.5;Y2.5;)S@drain_shared|ATTR_source_shared(D5G1;OJPX0.5;Y-2.5;)S@source_shared
INMOSwk;1{ic}|NMOSwk@0||17|-1||E|D0G4;|ATTR_Delay(D5G1;NPTX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||6|-16.5|4|2||
NOff-Page|conn@1||4.5|0|4|2||
NOff-Page|conn@2||-10|-8|4|2||
NWire_Pin|pin@0||0|-16.5|0.5|0.5||
NWire_Pin|pin@1||0|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@2||0|8.5|0|0|||ART_message(D5G6;)S[NMOSwk]
Awire|net@0||0|2700|pin@0||0|-16.5|NMOSfwk@0|s|0|-10
Awire|net@1||0|900|pin@1||0|0|NMOSfwk@0|d|0|-6
Awire|net@2||0|1800|conn@2|y|-8|-8|NMOSfwk@0|g|-3|-8
Awire|net@3||0|1800|pin@0||0|-16.5|conn@0|a|4|-16.5
Awire|net@4||0|1800|pin@1||0|0|conn@1|a|2.5|0
Ed|D5G2;|conn@1|y|B
Eg|D5G2;|conn@2|a|I
Es|D5G2;|conn@0|y|B
X

# Cell PMOS{ic}
CPMOS;1{ic}|artwork|1021415734000|1044914112000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-2|0|1|1|RR||ART_color()I10
Ngeneric:Invisible-Pin|pin@0||0|2|0|0||
Nschematic:Bus_Pin|pin@1||0|-2|0|0||
Nschematic:Bus_Pin|pin@2||-3|0|0|0||
NPin|pin@3||0|1|0|0||W
NPin|pin@4||-0.75|1|1|1||W
NPin|pin@5||-0.75|-1|1|1||W
NPin|pin@6||0|-1|0|0||W
NPin|pin@7||0|-2|0|0||W
NPin|pin@8||-3|0|0|0|RR|W
NPin|pin@9||-2.5|0|1|1|RRR|W
NPin|pin@10||0|2|0|0||W
NPin|pin@11||-1.5|1|1|1|Y|W
NPin|pin@12||-1.5|-1|1|1|Y|W
AThicker|net@0||0|FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I10
AThicker|net@1||0|FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I10
AThicker|net@2||0|FS1800|pin@8||-3|0|pin@9||-2.5|0|ART_color()I10
AThicker|net@3||0|FS2700|pin@3||0|1|pin@10||0|2|ART_color()I10
AThicker|net@4||0|FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I10
AThicker|net@5||0|FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I10
AThicker|net@6||0|FS2700|pin@12||-1.5|-1|pin@11||-1.5|1|ART_color()I10
Ed|D8G1;|pin@1||B
Eg|D6G1;|pin@2||I
Es|D2G1;|pin@0||B
X

# Cell PMOS{sch}
CPMOS;1{sch}|schematic|1021415734000|1098423037000||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_X(D5G1;HNPX-8.5;Y1.25;)I1|ATTR_drain_shared(D5G1;HNPX-8.5;Y-2.25;)I0|ATTR_source_shared(D5G1;HNPX-8.5;Y-3.75;)I0|prototype_center()I[0,0]
IPMOS;1{ic}|PMOS@0||20.75|13.5||E|D0G4;|ATTR_Delay(D5G1;NPTX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
IorangeGeneric180:PMOSf;1{ic}|PMOSf@0||0|7||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5G1;NOJPX3.5;)S@X == 0 ? 0 : @X < 0.5 ? (0.5 * (2 - 0.4) / @X + 0.4) : 2|ATTR_W(D6G1;NOJPX2;Y1;)S@X > 0.5 ? 6.0*@X : 3|ATTR_drain_shared(D5G1;OJPX0.5;Y-2.5;)S@drain_shared|ATTR_source_shared(D5G1;OJPX0.5;Y2.5;)S@source_shared
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||5|11.5|4|2||
NOff-Page|conn@1||-17.5|7|4|2||
NOff-Page|conn@2||5|1|4|2||
NWire_Pin|pin@1||0|11.5|0.5|0.5||
NWire_Pin|pin@2||0|1|0.5|0.5||
Ngeneric:Invisible-Pin|pin@3||-0.5|23.5|0|0|||ART_message(D5G6;)S[PMOS]
Ngeneric:Invisible-Pin|pin@4||-0.5|18.5|0|0|||ART_message(D5G2;)S[3 terminal strength-based PMOS device]
Awire|net@0||0|0|PMOSf@0|g|-3|7|conn@1|y|-15.5|7
Awire|net@1||0|900|pin@1||0|11.5|PMOSf@0|s|0|9
Awire|net@2||0|2700|pin@2||0|1|PMOSf@0|d|0|5
Awire|net@3||0|1800|pin@1||0|11.5|conn@0|a|3|11.5
Awire|net@4||0|0|conn@2|a|3|1|pin@2||0|1
Ed|D5G2;|conn@2|y|B
Eg|D5G2;|conn@1|a|I
Es|D5G2;|conn@0|y|B
X

# Cell PMOS4{ic}
CPMOS4;1{ic}|artwork|1021415734000|1085594360000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-2|0|1|1|RR||ART_color()I10
NPin|pin@0||0|0.5|0|0||W
NPin|pin@1||-0.75|0.5|1|1|Y|W
NPin|pin@2||-0.75|0.5|1|1|Y|W
NPin|pin@3||-0.5|0.25|1|1|YRR|W
NPin|pin@4||-0.75|0.5|1|1|Y|W
NPin|pin@5||-0.5|0.75|1|1|YRR|W
Nschematic:Bus_Pin|pin@6||0|0.5|2|2||
NPin|pin@7||-1.5|-1|1|1|Y|W
NPin|pin@8||-1.5|1|1|1|Y|W
NPin|pin@9||0|2|0|0||W
NPin|pin@10||-2.5|0|1|1|RRR|W
NPin|pin@11||-3|0|0|0|RR|W
NPin|pin@12||0|-2|0|0||W
NPin|pin@13||0|-1|0|0||W
NPin|pin@14||-0.75|-1|1|1||W
NPin|pin@15||-0.75|1|1|1||W
NPin|pin@16||0|1|0|0||W
Nschematic:Bus_Pin|pin@17||-3|0|0|0||
Nschematic:Bus_Pin|pin@18||0|-2|0|0||
Ngeneric:Invisible-Pin|pin@19||0|2|0|0||
AThicker|net@0||0|FS3150|pin@3||-0.5|0.25|pin@2||-0.75|0.5|ART_color()I10
AThicker|net@1||0|FS450|pin@5||-0.5|0.75|pin@4||-0.75|0.5|ART_color()I10
AThicker|net@2||0|FS0|pin@0||0|0.5|pin@1||-0.75|0.5|ART_color()I10
AThicker|net@3||0|FS2700|pin@7||-1.5|-1|pin@8||-1.5|1|ART_color()I10
AThicker|net@4||0|FS900|pin@15||-0.75|1|pin@14||-0.75|-1|ART_color()I10
AThicker|net@5||0|FS900|pin@13||0|-1|pin@12||0|-2|ART_color()I10
AThicker|net@6||0|FS2700|pin@16||0|1|pin@9||0|2|ART_color()I10
AThicker|net@7||0|FS1800|pin@11||-3|0|pin@10||-2.5|0|ART_color()I10
AThicker|net@8||0|FS1800|pin@14||-0.75|-1|pin@13||0|-1|ART_color()I10
AThicker|net@9||0|FS0|pin@16||0|1|pin@15||-0.75|1|ART_color()I10
Ed|D8G1;|pin@18||B
Eg|D6G1;|pin@17||I
Epower|D5G1;|pin@6||I
Es|D2G1;|pin@19||B
X

# Cell PMOS4{sch}
CPMOS4;1{sch}|schematic|1021415734000|1085691301000||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_X(D5G1;HNPX-8.5;Y1.25;)I1|prototype_center()I[0,0]
IPMOS4;1{ic}|PMOS4@0||18.75|14||E|D0G4;|ATTR_Delay(D5G1;NPTX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
IorangeGeneric180:PMOS4f;1{ic}|PMOS4f@0||0|7||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5G1;NOJPX3.5;)S@X == 0 ? 0 : @X < 0.25 ? (0.25 * (2 - 0.4) / @X + 0.4) : 2|ATTR_W(D6G1;NOJPX2;Y1;)S@X > 0.25 ? 6.0*@X : 3
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||12.5|7.5|4|2|YRR|
NOff-Page|conn@1||5|1|4|2||
NOff-Page|conn@2||-17.5|7|4|2||
NOff-Page|conn@3||5|11.5|4|2||
Ngeneric:Invisible-Pin|pin@0||-0.5|18.5|0|0|||ART_message(D5G2;)S[4 terminal strength-based PMOS device]
Ngeneric:Invisible-Pin|pin@1||-0.5|23.5|0|0|||ART_message(D5G6;)S[PMOS4]
NWire_Pin|pin@2||0|1|0.5|0.5||
NWire_Pin|pin@3||0|11.5|0.5|0.5||
Awire|net@0||0|1800|PMOS4f@0|b|0|7.5|conn@0|y|10.5|7.5
Awire|net@1||0|900|pin@3||0|11.5|PMOS4f@0|s|0|9
Awire|net@2||0|0|PMOS4f@0|g|-3|7|conn@2|y|-15.5|7
Awire|net@3||0|2700|pin@2||0|1|PMOS4f@0|d|0|5
Awire|net@4||0|0|conn@1|a|3|1|pin@2||0|1