orangegeneric180.jelib

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

Awire|net@5||0|2700|pin@1||0|1|pmos4p@0|d|0|5
Eb|D5G2;|conn@1|y|B
Ed|D5G2;|conn@3|y|B
Eg|D5G2;|conn@2|a|I
Es|D5G2;|conn@0|y|B
X

# Cell PMOS4fwk{ic}
CPMOS4fwk;1{ic}|artwork|1021415734000|1098422023000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-1.5|0|0.5|0.5|RR||ART_color()I74
Nschematic:Bus_Pin|pin@0||0|0.5|0|0||
NPin|pin@1||-0.75|0.5|1|1|Y|W
NPin|pin@2||0|0.5|0|0||W
NPin|pin@3||-0.5|0.25|1|1|YRR|W
NPin|pin@4||-0.75|0.5|1|1|Y|W
NPin|pin@5||-0.5|0.75|1|1|YRR|W
NPin|pin@6||-0.75|0.5|1|1|Y|W
NPin|pin@7||-1.25|-0.75|1|1|Y|W
NPin|pin@8||-1.25|0.75|1|1|Y|W
NPin|pin@9||0|2|0|0||W
NPin|pin@10||-1.75|0|1|1|RRR|W
NPin|pin@11||-3|0|0|0|RR|W
NPin|pin@12||0|-2|0|0||W
NPin|pin@13||0|-0.75|0|0||W
NPin|pin@14||-0.75|-0.75|1|1||W
NPin|pin@15||-0.75|0.75|1|1||W
NPin|pin@16||0|0.75|0|0||W
Nschematic:Bus_Pin|pin@17||-3|0|0|0||
Nschematic:Bus_Pin|pin@18||0|-2|0|0||
Ngeneric:Invisible-Pin|pin@19||0|2|0|0||
Ngeneric:Invisible-Pin|pin@20||-0.5|0|0|0|||ART_message(D5G1;)S[wk]
AThicker|net@0||0|FS0|pin@2||0|0.5|pin@1||-0.75|0.5|ART_color()I74
AThicker|net@1||0|FS3150|pin@3||-0.5|0.25|pin@4||-0.75|0.5|ART_color()I74
AThicker|net@2||0|FS450|pin@5||-0.5|0.75|pin@6||-0.75|0.5|ART_color()I74
AThicker|net@3||0|FS2700|pin@7||-1.25|-0.75|pin@8||-1.25|0.75|ART_color()I74
AThicker|net@4||0|FS900|pin@15||-0.75|0.75|pin@14||-0.75|-0.75|ART_color()I74
AThicker|net@5||0|FS900|pin@13||0|-0.75|pin@12||0|-2|ART_color()I74
AThicker|net@6||0|FS2700|pin@16||0|0.75|pin@9||0|2|ART_color()I74
AThicker|net@7||0|FS1800|pin@11||-3|0|pin@10||-1.75|0|ART_color()I74
AThicker|net@8||0|FS1800|pin@14||-0.75|-0.75|pin@13||0|-0.75|ART_color()I74
AThicker|net@9||0|FS0|pin@16||0|0.75|pin@15||-0.75|0.75|ART_color()I74
Eb|D5G1;|pin@0||B
Ed|D8G1;|pin@18||B
Eg|D6G1;|pin@17||I
Es|D2G1;|pin@19||B
X

# Cell PMOS4fwk{sch}
CPMOS4fwk;1{sch}|schematic|1021415734000|1098423662000||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_L(D5G1;HNPX-8.5;Y1.25;)I2|ATTR_SPICE_template(D5G1;NTX1.5;Y-8;)SM$(node_name) $(d) $(g) $(s) $(b) P W='$(W)' L='$(L)' AD='2*$(W)*hdifp/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifp/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifp/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifp/0.1u)/($(source_shared)+1)'|ATTR_W(D5G1;HNPX-8.75;Y3;)I3|ATTR_drain_shared(D5G1;HNPX-8.5;Y-2.25;)I0|ATTR_source_shared(D5G1;HNPX-8.5;Y-3.75;)I0|ATTR_verilog_template(D5G1;NTX-7.5;Y-10;)Srtranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
IPMOS4fwk;1{ic}|PMOS4fwk@0||23.25|19.5||E|D0G4;|ATTR_Delay(D5G1;NTX3.5;Y-2;)I100|ATTR_L(D5G1;NTX3.5;)I2|ATTR_W(D6G1;NTX2;Y1;)I3|ATTR_drain_shared(D5G1;X0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;X0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||5|8|4|2||
NOff-Page|conn@1||5|1|4|2||
NOff-Page|conn@2||-8|7|4|2||
NOff-Page|conn@3||5|11.5|4|2||
Ngeneric:Invisible-Pin|pin@0||-1.5|19.5|0|0|||ART_message(D5G2;)S[weak 4 terminal PMOS device]
Ngeneric:Invisible-Pin|pin@1||-1|23|0|0|||ART_message(D5G6;)S[PMOSwk]
NWire_Pin|pin@2||0|1|0.5|0.5||
NWire_Pin|pin@3||0|11.5|0.5|0.5||
N4-Port-Transistor|pmos4p@0||-2|7|4|4|YR|2|ATTR_length(D5G1;OJX1.5;)S"P(\"L\")"|ATTR_width(D5G1.5;OJX-0.5;Y-2;)S"P(\"W\")"|SIM_weak_node(D5G1;)SWeak
Awire|net@0||0|1800|pmos4p@0|b|0|8|conn@0|a|3|8
Awire|net@1||0|1800|conn@2|y|-6|7|pmos4p@0|g|-3|7
Awire|net@2||0|2700|pin@2||0|1|pmos4p@0|d|0|5
Awire|net@3||0|0|conn@1|a|3|1|pin@2||0|1
Awire|net@4||0|2700|pmos4p@0|s|0|9|pin@3||0|11.5
Awire|net@5||0|1800|pin@3||0|11.5|conn@3|a|3|11.5
Eb|D5G2;|conn@0|y|B
Ed|D5G2;|conn@1|y|B
Eg|D5G2;|conn@2|a|I
Es|D5G2;|conn@3|y|B
X

# Cell PMOSf{ic}
CPMOSf;1{ic}|artwork|1021415734000|1046821723000|E|prototype_center()I[-8000,16000]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-2|0|1|1|RR||ART_color()I74
Ngeneric:Invisible-Pin|pin@0||0|2|0|0||
Nschematic:Bus_Pin|pin@1||0|-2|0|0||
Nschematic:Bus_Pin|pin@2||-3|0|0|0||
NPin|pin@3||0|1|0|0||W
NPin|pin@4||-0.75|1|1|1||W
NPin|pin@5||-0.75|-1|1|1||W
NPin|pin@6||0|-1|0|0||W
NPin|pin@7||0|-2|0|0||W
NPin|pin@8||-3|0|0|0|RR|W
NPin|pin@9||-2.5|0|1|1|RRR|W
NPin|pin@10||0|2|0|0||W
NPin|pin@11||-1.5|1|1|1|Y|W
NPin|pin@12||-1.5|-1|1|1|Y|W
AThicker|net@0||0|FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I74
AThicker|net@1||0|FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I74
AThicker|net@2||0|FS1800|pin@8||-3|0|pin@9||-2.5|0|ART_color()I74
AThicker|net@3||0|FS2700|pin@3||0|1|pin@10||0|2|ART_color()I74
AThicker|net@4||0|FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I74
AThicker|net@5||0|FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I74
AThicker|net@6||0|FS2700|pin@12||-1.5|-1|pin@11||-1.5|1|ART_color()I74
Ed|D8G1;|pin@1||B
Eg|D6G1;|pin@2||I
Es|D2G1;|pin@0||B
X

# Cell PMOSf{sch}
CPMOSf;1{sch}|schematic|1021415734000|1098422784000||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_L(D5G1;HNPX-8.5;Y1.25;)I2|ATTR_SPICE_template(D5G1;NTX3;Y-10.5;)SM$(node_name) $(d) $(g) $(s) vdd P W='$(W)' L='$(L)' AD='2*$(W)*hdifp/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifp/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifp/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifp/0.1u)/($(source_shared)+1)'|ATTR_W(D5G1;HNPX-8.75;Y3;)I3|ATTR_drain_shared(D5G1;HNPX-8.5;Y-1.75;)I0|ATTR_source_shared(D5G1;HNPX-8.5;Y-3.25;)I0|ATTR_verilog_template(D5G1;NTX-3.5;Y-12.5;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
IPMOSf;1{ic}|PMOSf@0||30.25|21.5||E|D0G4;|ATTR_Delay(D5G1;NTX3.5;Y-2;)I100|ATTR_L(D5G1;NTX3.5;)I2|ATTR_W(D6G1;NTX2;Y1;)I3|ATTR_drain_shared(D5G1;X0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;X0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||8|12.5|4|2||
NOff-Page|conn@1||-25|7|4|2||
NOff-Page|conn@2||8.5|0|4|2||
NWire_Pin|pin@0||0|12.5|0.5|0.5||
NWire_Pin|pin@1||0|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@2||-0.5|23.5|0|0|||ART_message(D5G6;)S[PMOSf]
Ngeneric:Invisible-Pin|pin@3||-0.5|18.5|0|0|||ART_message(D5G2;)S[4 terminal lambda-based PMOS device]
N4-Port-Transistor|pmos4p@0||-2|7|4|4|YR|2|ATTR_length(D5G1;OJX1.5;)S"P(\"L\")"|ATTR_width(D5G1.5;OJX-0.5;Y-2;)S"P(\"W\")"
NPower|pwr@0||6|8|3|3||
Awire|net@0||0|0|conn@2|a|6.5|0|pin@1||0|0
Awire|net@1||0|0|pmos4p@0|g|-3|7|conn@1|y|-23|7
Awire|net@2||0|0|conn@0|a|6|12.5|pin@0||0|12.5
Awire|net@3||0|2700|pmos4p@0|s|0|9|pin@0||0|12.5
Awire|net@4||0|2700|pin@1||0|0|pmos4p@0|d|0|5
Awire|net@5||0|1800|pmos4p@0|b|0|8|pwr@0||6|8
Ed|D5G2;|conn@2|y|B
Eg|D5G2;|conn@1|a|I
Es|D5G2;|conn@0|y|B
X

# Cell PMOSfwk{ic}
CPMOSfwk;1{ic}|artwork|1021415734000|1047945019000|E|prototype_center()I[-8000,16000]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-1.5|0|0.5|0.5|RR||ART_color()I74
Ngeneric:Invisible-Pin|pin@0||-0.5|0|0|0|||ART_message(D5G1;)S[wk]
Ngeneric:Invisible-Pin|pin@1||0|2|0|0||
Nschematic:Bus_Pin|pin@2||0|-2|0|0||
Nschematic:Bus_Pin|pin@3||-3|0|0|0||
NPin|pin@4||0|0.75|0|0||W
NPin|pin@5||-0.75|0.75|1|1||W
NPin|pin@6||-0.75|-0.75|1|1||W
NPin|pin@7||0|-0.75|0|0||W
NPin|pin@8||0|-2|0|0||W
NPin|pin@9||-3|0|0|0|RR|W
NPin|pin@10||-1.75|0|1|1|RRR|W
NPin|pin@11||0|2|0|0||W
NPin|pin@12||-1.25|0.75|1|1|Y|W
NPin|pin@13||-1.25|-0.75|1|1|Y|W
AThicker|net@0||0|FS0|pin@4||0|0.75|pin@5||-0.75|0.75|ART_color()I74
AThicker|net@1||0|FS1800|pin@6||-0.75|-0.75|pin@7||0|-0.75|ART_color()I74
AThicker|net@2||0|FS1800|pin@9||-3|0|pin@10||-1.75|0|ART_color()I74
AThicker|net@3||0|FS2700|pin@4||0|0.75|pin@11||0|2|ART_color()I74
AThicker|net@4||0|FS900|pin@7||0|-0.75|pin@8||0|-2|ART_color()I74
AThicker|net@5||0|FS900|pin@5||-0.75|0.75|pin@6||-0.75|-0.75|ART_color()I74
AThicker|net@6||0|FS2700|pin@13||-1.25|-0.75|pin@12||-1.25|0.75|ART_color()I74
Ed|D8G1;|pin@2||B
Eg|D6G1;|pin@3||I
Es|D2G1;|pin@1||B
X

# Cell PMOSfwk{sch}
CPMOSfwk;1{sch}|schematic|1021415734000|1098423644000||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_L(D5G1;HNPX-8.5;Y1.25;)I2|ATTR_SPICE_template(D5G1;NTX2.5;Y-12.5;)SM$(node_name) $(d) $(g) $(s) vdd P W='$(W)' L='$(L)' AD='2*$(W)*hdifp/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifp/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifp/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifp/0.1u)/($(source_shared)+1)'|ATTR_W(D5G1;HNPX-8.75;Y3;)I3|ATTR_drain_shared(D5G1;HNPX-8.5;Y-2.25;)I0|ATTR_source_shared(D5G1;HNPX-9;Y-3.75;)I0|ATTR_verilog_template(D5G1;NTX-2.5;Y-14.5;)Srtranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
IPMOSfwk;1{ic}|PMOSfwk@0||27.25|16.5||E|D0G4;|ATTR_Delay(D5G1;NTX3.5;Y-2;)I100|ATTR_L(D5G1;NTX3.5;)I2|ATTR_M(T)I1|ATTR_W(D6G1;NTX2;Y1;)I3|ATTR_drain_shared(D5G1;X0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;X0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||5|11.5|4|2||
NOff-Page|conn@1||-8|7|4|2||
NOff-Page|conn@2||5|1|4|2||
NWire_Pin|pin@0||0|11.5|0.5|0.5||
NWire_Pin|pin@1||0|1|0.5|0.5||
Ngeneric:Invisible-Pin|pin@2||-1|23|0|0|||ART_message(D5G6;)S[PMOSwk]
Ngeneric:Invisible-Pin|pin@3||-1.5|19.5|0|0|||ART_message(D5G2;)S[4 terminal lambda-based weak PMOS device]
N4-Port-Transistor|pmos4p@0||-2|7|4|4|YR|2|ATTR_length(D5G1;OJX1.5;)S"P(\"L\")"|ATTR_width(D5G1.5;OJX-0.5;Y-2;)S"P(\"W\")"
NPower|pwr@0||6|8|3|3||
Awire|net@0||0|1800|pin@0||0|11.5|conn@0|a|3|11.5
Awire|net@1||0|2700|pmos4p@0|s|0|9|pin@0||0|11.5
Awire|net@2||0|0|conn@2|a|3|1|pin@1||0|1
Awire|net@3||0|2700|pin@1||0|1|pmos4p@0|d|0|5
Awire|net@4||0|1800|conn@1|y|-6|7|pmos4p@0|g|-3|7
Awire|net@5||0|1800|pmos4p@0|b|0|8|pwr@0||6|8
Ed|D5G2;|conn@2|y|B
Eg|D5G2;|conn@1|a|I
Es|D5G2;|conn@0|y|B
X

# Cell wire{ic}
Cwire;1{ic}|artwork|1083964052000|1083971272000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-2|0|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
NThick-Circle|art@2||2|0|1.5|1.5|||ART_color()I74
NPin|pin@0||-2.75|0|1|1||W
NPin|pin@1||-4|0|0|0||W
NPin|pin@2||2|0|1|1||W
NPin|pin@3||4|0|0|0||W
NPin|pin@4||-2|0.75|1|1||W
NPin|pin@5||2|0.75|1|1||W
NPin|pin@6||2|-0.75|1|1||W
NPin|pin@7||-2|-0.75|1|1||W
Nschematic:Bus_Pin|pin@8||4|0|0|0||
Nschematic:Bus_Pin|pin@9||-4|0|0|0||
AThicker|net@0||0|IJS0|pin@0||-2.75|0|pin@1||-4|0|ART_color()I74
AThicker|net@1||0|IJS1800|pin@2||2|0|pin@3||4|0|ART_color()I74
AThicker|net@2||0|IJS0|pin@5||2|0.75|pin@4||-2|0.75|ART_color()I74
AThicker|net@3||0|IJS0|pin@6||2|-0.75|pin@7||-2|-0.75|ART_color()I74
Ea|D5G2;|pin@9||U
Eb|D5G2;|pin@8||U
X

# Cell wire{sch}
Cwire;1{sch}|schematic|1083961993000|1084405246000||ATTR_C(D5G1;HNPUCX-19;Y-9;)S0.020f|ATTR_L(D5G1;HNPUDX-19;Y-7;)I100|ATTR_R(D5G1;HNPURX-19;Y-8;)S15m|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NCapacitor|cap@0||-10|0|3|4|||SCHEM_capacitance(D5G1;OJUC)S@C*@L/3
NCapacitor|cap@1||10|0|3|4|||SCHEM_capacitance(D5G1;OJUC)S@C*@L/3
NCapacitor|cap@2||0|0|3|4|||SCHEM_capacitance(D5G1;OJUC)S@C*@L/3
NOff-Page|conn@0||21|4|4|2|RR|
NOff-Page|conn@1||-21|4|4|2||
NGround|gnd@0||0|-8|3|4||
Ngeneric:Invisible-Pin|pin@0||15|7|0|0|||ART_message(D5G1;)S[R2 ]
Ngeneric:Invisible-Pin|pin@1||-15|7|0|0|||ART_message(D5G1;)S[R1 = @R*@L/6]
Ngeneric:Invisible-Pin|pin@2||0|7|0|0|||ART_message(D5G1;)S[R12= @R*@L/3]
Ngeneric:Invisible-Pin|pin@3||16.5|-2|0|0|||ART_message(D5G1;)S[C = @C*@L/3]
Ngeneric:Invisible-Pin|pin@4||0|14|0|0|||ART_message(D5G2;)S[this is a wire 'L' lambda long,with resistance 'R' ohms/lambda,and capacitance 'C' F/lambda]
Ngeneric:Invisible-Pin|pin@5||-1|22|0|0|||ART_message(D5G6;)S[wire]
NWire_Pin|pin@6||0|-4|0.5|0.5||
NWire_Pin|pin@7||10|-4|0.5|0.5||
NWire_Pin|pin@8||-10|-4|0.5|0.5||
NWire_Pin|pin@9||10|4|0.5|0.5||
NWire_Pin|pin@10||0|4|0.5|0.5||
NWire_Pin|pin@11||-10|4|0.5|0.5||
NResistor|res@0||-15|4|6|1|||SCHEM_resistance(D5G1;OJURY1.5;)S@R*@L/6
NResistor|res@1||-5|4|6|1|||SCHEM_resistance(D5G1;OJURY1.5;)S@R*@L/3
NResistor|res@2||15|4|6|1|||SCHEM_resistance(D5G1;OJURY1.5;)S@R*@L/6
NResistor|res@3||5|4|6|1|||SCHEM_resistance(D5G1;OJURY1.5;)S@R*@L/3
Iwire;1{ic}|wire@0||15|24||E|D0G4;|ATTR_C(D5G1;NUCY-2.5;)F2.23E-16|ATTR_L(D5G1;UD)I100|ATTR_R(D5G1;NURY-1.5;)F0.24
Awire|net@0||0|IJS1800|res@2|b|17|4|conn@0|y|19|4
Awire|net@1||0|IJS0|res@0|a|-17|4|conn@1|y|-19|4
Awire|net@2||0|IJS900|pin@6||0|-4|gnd@0||0|-6
Awire|net@3||0|IJS2700|pin@6||0|-4|cap@2|b|0|-2
Awire|net@4||0|IJS0|pin@7||10|-4|pin@6||0|-4
Awire|net@5||0|IJS0|pin@6||0|-4|pin@8||-10|-4
Awire|net@6||0|IJS900|cap@1|b|10|-2|pin@7||10|-4
Awire|net@7||0|IJS2700|pin@8||-10|-4|cap@0|b|-10|-2
Awire|net@8||0|IJS900|pin@9||10|4|cap@1|a|10|2
Awire|net@9||0|IJS0|res@2|a|13|4|pin@9||10|4
Awire|net@10||0|IJS0|pin@9||10|4|res@3|b|7|4
Awire|net@11||0|IJS900|pin@10||0|4|cap@2|a|0|2
Awire|net@12||0|IJS0|res@3|a|3|4|pin@10||0|4
Awire|net@13||0|IJS0|pin@10||0|4|res@1|b|-3|4
Awire|net@14||0|IJS900|pin@11||-10|4|cap@0|a|-10|2
Awire|net@15||0|IJS0|res@1|a|-7|4|pin@11||-10|4
Awire|net@16||0|IJS0|pin@11||-10|4|res@0|b|-13|4
Ea|D4G2;|conn@1|a|U
Eb|D6G2;X-5;|conn@0|y|U
X

# Cell wire180{ic}
Cwire180;1{ic}|artwork|1083966364000|1084405602000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-1.75|0|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
NThick-Circle|art@2||1.75|0|1.5|1.5|RRR||ART_color()I74|ART_degrees()F[0.0,3.1415927]
NPin|pin@0||-1.75|0.75|1|1||W
NPin|pin@1||1.75|0.75|1|1||W
NPin|pin@2||1.75|-0.75|1|1||W
NPin|pin@3||-1.75|-0.75|1|1||W
Nschematic:Bus_Pin|pin@4||2.5|0|1|1||
Nschematic:Bus_Pin|pin@5||-2.5|0|1|1||
AThicker|net@0||0|FS0|pin@1||1.75|0.75|pin@0||-1.75|0.75|ART_color()I74
AThicker|net@1||0|FS0|pin@2||1.75|-0.75|pin@3||-1.75|-0.75|ART_color()I74
Ea|D5G2;|pin@5||B
Eb|D5G2;|pin@4||B
X

# Cell wire180{sch}
Cwire180;1{sch}|schematic|1083965121000|1119463992509||ATTR_L(D5G1;HNPUDX-20.5;Y-6.5;)I100|ATTR_LEWIRE(D5G1;HNPTX-20.5;Y-9.5;)I1|ATTR_layer(D5G1;HNPX-20.5;Y-7.5;)I1|ATTR_width(D5G1;HNPX-20.5;Y-8.5;)I3|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||-23|-1|4|2||
NOff-Page|conn@1||-5.5|-1|4|2|YRR|
Ngeneric:Invisible-Pin|pin@0||-5.5|9.5|0|0|||ART_message(BD5G2;)S[wire180]
Ngeneric:Invisible-Pin|pin@1||7|-8|0|0|||ART_message(D5G1;)SR = (@layer==0?5:0.045)/@width
Ngeneric:Invisible-Pin|pin@2||7|-6|0|0|||ART_message(D5G1;)SC = [(@layer==0?15:20)+(@width-3)] aF/lambda
Ngeneric:Invisible-Pin|pin@3||-14|6|0|0|||ART_message(D6G1;)S["wire in layer 'layer', 'L' lambda long,","'width' lambda wide, for the 180nm tech"]
Ngeneric:Invisible-Pin|pin@4||-10|3.5|0|0|||ART_message(D6G1;)Slayer=0 is for poly
Ngeneric:Invisible-Pin|pin@5||7|-10|0|0|||ART_message(D5G1;)SLEWIRECAP = C * L
Iwire180;1{ic}|wire180@0||14|7.88||E|D0G4;|ATTR_L(D5G1;UD)I100|ATTR_LEWIRE()I1|ATTR_layer(D5G1;NY-1;)I1|ATTR_width(D5G1;NY-2;)I3
Iwire;1{ic}|wire@0||-15|-1||E|D0G4;|ATTR_C(D5G1;NOJUCY-2.5;)S((@layer==0?15:20)+(@width-3))*1e-18|ATTR_L(D5G1;OJUD)S@L|ATTR_LEWIRECAP(D5G1;NOJTUDX-5.5;Y-9.5;)S((@layer==0?15:20)+(@width-3))*1e-18*@L|ATTR_R(D5G1;NOJURY-1.5;)S(@layer==0?5:0.045)/@width
Awire|net@0||0|0|wire@0|a|-19|-1|conn@0|y|-21|-1
Awire|net@1||0|1800|wire@0|b|-11|-1|conn@1|y|-7.5|-1
Ea|D4G2;|conn@0|a|B
Eb|D4G2;|conn@1|a|B
X

# Groups:
GNMOS4f;1{sch}|NMOS4f;1{ic}
GNMOS4fwk;1{sch}|NMOS4fwk;1{ic}
GNMOSf;1{sch}|NMOSf;1{ic}
GNMOSfwk;1{sch}|NMOSfwk;1{ic}
GPMOS4f;1{sch}|PMOS4f;1{ic}
GPMOS4fwk;1{sch}|PMOS4fwk;1{ic}
GPMOSf;1{sch}|PMOSf;1{ic}
GPMOSfwk;1{sch}|PMOSfwk;1{ic}
Gwire;1{sch}|wire;1{ic}
Gwire180;1{sch}|wire180;1{ic}