orangegeneric180.jelib

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

# header information:
HorangeGeneric180|8.02p|USER_electrical_units()I70464

# Views:
Vicon|ic
Vschematic|sch

# Technologies:
Tartwork
Tgeneric
Tmocmos
Tschematic

# Cell NMOS4f{ic}
CNMOS4f;1{ic}|artwork|1021415734000|1046880615000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NPin|pin@0||-0.25|-0.75|0|0||W
NPin|pin@1||-0.25|-0.25|0|0||W
NPin|pin@2||-0.75|-0.5|1|1|RR|W
NPin|pin@3||0|-0.5|0|0|RR|W
Ngeneric:Invisible-Pin|pin@4||0|-0.5|0|0||
Ngeneric:Invisible-Pin|pin@5||0|-2|0|0||
NPin|pin@6||-1.5|0|1|1|RR|W
NPin|pin@7||-3|0|0|0|RR|W
Nschematic:Bus_Pin|pin@8||-3|0|0|0||
Nschematic:Bus_Pin|pin@9||0|2|0|0||
NPin|pin@10||0|-2|0|0||W
NPin|pin@11||-1.5|1|1|1||W
NPin|pin@12||-1.5|-1|1|1||W
NPin|pin@13||0|-1|0|0||W
NPin|pin@14||-0.75|-1|1|1||W
NPin|pin@15||-0.75|1|1|1||W
NPin|pin@16||0|1|0|0||W
NPin|pin@17||0|2|0|0||W
AThicker|net@0||0|FS2250|pin@0||-0.25|-0.75|pin@3||0|-0.5|ART_color()I74
AThicker|net@1||0|FS1350|pin@1||-0.25|-0.25|pin@3||0|-0.5|ART_color()I74
AThicker|net@2||0|FS1800|pin@2||-0.75|-0.5|pin@3||0|-0.5|ART_color()I74
AThicker|net@3||0|FS900|pin@15||-0.75|1|pin@14||-0.75|-1|ART_color()I74
AThicker|net@4||0|FS1800|pin@7||-3|0|pin@6||-1.5|0|ART_color()I74
AThicker|net@5||0|FS900|pin@11||-1.5|1|pin@12||-1.5|-1|ART_color()I74
AThicker|net@6||0|FS900|pin@13||0|-1|pin@10||0|-2|ART_color()I74
AThicker|net@7||0|FS1800|pin@14||-0.75|-1|pin@13||0|-1|ART_color()I74
AThicker|net@8||0|FS0|pin@16||0|1|pin@15||-0.75|1|ART_color()I74
AThicker|net@9||0|FS900|pin@17||0|2|pin@16||0|1|ART_color()I74
Eb|D5G1;|pin@4||B
Ed|D5G1;|pin@9||B
Eg|D5G1;|pin@8||I
Es|D5G1;|pin@5||B
X

# Cell NMOS4f{sch}
CNMOS4f;1{sch}|schematic|1021415734000|1098400354000||ATTR_Delay(D5G1;HNPX-18.25;Y-12.5;)I100|ATTR_L(D5G1;HNPX-18;Y-11.5;)I2|ATTR_SPICE_template(D5G1;NTX-2.5;Y-19.5;)SM$(node_name) $(d) $(g) $(s) $(b) N W='$(W)' L='$(L)' AD='2*$(W)*hdifn/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifn/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifn/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifn/0.1u)/($(source_shared)+1)'|ATTR_W(D5G1;HNPX-18;Y-10.5;)I3|ATTR_drain_shared(D5G1;HNPX-18.5;Y-13.75;)I0|ATTR_source_shared(D5G1;HNPX-18.5;Y-14.75;)I0|ATTR_verilog_template(D5G1;NTX-6;Y-21.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
INMOS4f;1{ic}|NMOS4f@0||23.5|3.5||E|D0G4;|ATTR_Delay(D5G1;NTX3.25;Y-2.25;)I100|ATTR_L(D5G1;NX3.25;Y-0.25;)I2|ATTR_W(D6G1;NX1.75;Y0.75;)I3|ATTR_drain_shared(D5G1;X0.5;Y2.5;)I0|ATTR_source_shared(D5G1;X0.5;Y-2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||4.5|-7.5|4|2||
NOff-Page|conn@1||4.5|-12.5|4|2||
NOff-Page|conn@2||4.5|0|4|2||
NOff-Page|conn@3||-18.5|-6.5|4|2||
N4-Port-Transistor|nmos4p@0||-2|-6.5|4|4|R||ATTR_length(D5G1;OJ)S"P(\"L\")"|ATTR_width(D5G1.5;OJX0.5;Y-1;)S"P(\"W\")"
Ngeneric:Invisible-Pin|pin@0||-2|6.5|0|0|||ART_message(D5G3;)S[4 terminal device]
NWire_Pin|pin@1||0|-12.5|0.5|0.5||
NWire_Pin|pin@2||0|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@3||-1.5|11|0|0|||ART_message(D5G6;)S[NMOS4f]
Awire|net@0||0|0|nmos4p@0|g|-3|-6.5|conn@3|y|-16.5|-6.5
Awire|net@1||0|1800|nmos4p@0|b|0|-7.5|conn@0|a|2.5|-7.5
Awire|net@2||0|900|nmos4p@0|s|0|-8.5|pin@1||0|-12.5
Awire|net@3||0|1800|pin@1||0|-12.5|conn@1|a|2.5|-12.5
Awire|net@4||0|1800|pin@2||0|0|conn@2|a|2.5|0
Awire|net@5||0|900|pin@2||0|0|nmos4p@0|d|0|-4.5
Eb|D5G2;|conn@0|y|B
Ed|D5G2;|conn@2|y|B
Eg|D5G2;|conn@3|a|I
Es|D5G2;|conn@1|y|B
X

# Cell NMOS4fwk{ic}
CNMOS4fwk;1{ic}|artwork|1021415734000|1098403749000|E|prototype_center()I[0,-8000]
Ngeneric:Facet-Center|art@0||0|0|0|0|R|AV
NPin|pin@0||0|2|0|0||W
NPin|pin@1||0|0.75|0|0||W
NPin|pin@2||-0.75|0.75|1|1||W
NPin|pin@3||-0.75|-0.75|1|1||W
NPin|pin@4||0|-0.75|0|0||W
NPin|pin@5||-1.25|-0.75|1|1||W
NPin|pin@6||-1.25|0.75|1|1||W
NPin|pin@7||0|-2|0|0||W
Nschematic:Bus_Pin|pin@8||0|2|0|0||
Nschematic:Bus_Pin|pin@9||-3|0|0|0||
NPin|pin@10||-3|0|0|0|RR|W
NPin|pin@11||-1.25|0|1|1|RR|W
Ngeneric:Invisible-Pin|pin@12||0|-2|0|0||
Ngeneric:Invisible-Pin|pin@13||-0.5|0|0|0|||ART_message(D5G1;)S[wk]
NPin|pin@14||0|-0.5|0|0||W
NPin|pin@15||-0.75|-0.5|1|1||W
NPin|pin@16||-0.5|-0.75|1|1|YRR|W
NPin|pin@17||-0.75|-0.5|1|1|Y|W
NPin|pin@18||-0.75|-0.5|1|1||W
NPin|pin@19||-0.5|-0.25|1|1|RR|W
Nschematic:Bus_Pin|pin@20||0|-0.5|0|0||
AThicker|net@0||0|FS900|pin@0||0|2|pin@1||0|0.75|ART_color()I74
AThicker|net@1||0|FS0|pin@1||0|0.75|pin@2||-0.75|0.75|ART_color()I74
AThicker|net@2||0|FS1800|pin@3||-0.75|-0.75|pin@4||0|-0.75|ART_color()I74
AThicker|net@3||0|FS900|pin@4||0|-0.75|pin@7||0|-2|ART_color()I74
AThicker|net@4||0|FS900|pin@6||-1.25|0.75|pin@5||-1.25|-0.75|ART_color()I74
AThicker|net@5||0|FS1800|pin@10||-3|0|pin@11||-1.25|0|ART_color()I74
AThicker|net@6||0|FS900|pin@2||-0.75|0.75|pin@3||-0.75|-0.75|ART_color()I74
AThicker|net@7||0|FS1800|pin@15||-0.75|-0.5|pin@14||0|-0.5|ART_color()I74
AThicker|net@8||0|FS3150|pin@16||-0.5|-0.75|pin@17||-0.75|-0.5|ART_color()I74
AThicker|net@9||0|FS450|pin@19||-0.5|-0.25|pin@18||-0.75|-0.5|ART_color()I74
Eb|D5G1;|pin@20||B
Ed|D5G1;|pin@8||B
Eg|D5G1;|pin@9||I
Es|D5G1;|pin@12||B
X

# Cell NMOS4fwk{sch}
CNMOS4fwk;1{sch}|schematic|1021415734000|1047947164000||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5G1;HNPX-9;Y-13.5;)I2|ATTR_SPICE_template(D5G1;NTX0.5;Y-24;)SM$(node_name) $(d) $(g) $(s) $(b) N W='$(W)' L='$(L)' AD='2*$(W)*hdifn/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifn/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifn/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifn/0.1u)/($(source_shared)+1)'|ATTR_W(D5G1;HNPX-8.5;Y-12.5;)I3|ATTR_drain_shared(D5G1;HNPX-8.5;Y-16.25;)I0|ATTR_source_shared(D5G1;HNPX-8.5;Y-17.75;)I0|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Srtranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
INMOS4fwk;1{ic}|NMOS4fwk@0||17|-1||E|D0G4;|ATTR_Delay(D5G1;NTX3.5;Y-2;)I100|ATTR_L(D5G1;NTX3.5;)I2|ATTR_M(T)I1|ATTR_W(D6G1;NTX2;Y1;)I3|ATTR_drain_shared(D5G1;X0.5;Y2.5;)I0|ATTR_source_shared(D5G1;X0.5;Y-2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||-10|-8|4|2||
NOff-Page|conn@1||4.5|0|4|2||
NOff-Page|conn@2||6|-16.5|4|2||
NOff-Page|conn@3||6|-9|4|2|YRR|
N4-Port-Transistor|nmos4p@0||-2|-8|4|4|R||ATTR_length(D5G1;OJ)S"P(\"L\")"|ATTR_width(D5G1.5;OJX0.5;Y-1;)S"P(\"W\")"
Ngeneric:Invisible-Pin|pin@0||0|8.5|0|0|||ART_message(D5G6;)S[NMOS4fwk]
NWire_Pin|pin@1||0|0|0.5|0.5||
NWire_Pin|pin@2||0|-16.5|0.5|0.5||
Awire|net@0||0|900|pin@1||0|0|nmos4p@0|d|0|-6
Awire|net@1||0|1800|conn@0|y|-8|-8|nmos4p@0|g|-3|-8
Awire|net@2||0|1800|pin@1||0|0|conn@1|a|2.5|0
Awire|net@3||0|1800|pin@2||0|-16.5|conn@2|a|4|-16.5
Awire|net@4||0|900|nmos4p@0|s|0|-10|pin@2||0|-16.5
Awire|net@5||0|1800|nmos4p@0|b|0|-9|conn@3|y|4|-9
Eb|D5G2;|conn@3|y|B
Ed|D5G2;|conn@1|y|B
Eg|D5G2;|conn@0|a|I
Es|D5G2;|conn@2|y|B
X

# Cell NMOSf{ic}
CNMOSf;1{ic}|artwork|1021415734000|1046884569000|E|prototype_center()I[0,-8000]
Ngeneric:Facet-Center|art@0||0|0|0|0|R|AV
Ngeneric:Invisible-Pin|pin@0||0|-2|0|0||
NPin|pin@1||-1.5|0|1|1|RR|W
NPin|pin@2||-3|0|0|0|RR|W
Nschematic:Bus_Pin|pin@3||-3|0|0|0||
Nschematic:Bus_Pin|pin@4||0|2|0|0||
NPin|pin@5||0|-2|0|0||W
NPin|pin@6||-1.5|1|1|1||W
NPin|pin@7||-1.5|-1|1|1||W
NPin|pin@8||0|-1|0|0||W
NPin|pin@9||-0.75|-1|1|1||W
NPin|pin@10||-0.75|1|1|1||W
NPin|pin@11||0|1|0|0||W
NPin|pin@12||0|2|0|0||W
AThicker|net@0||0|FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
AThicker|net@1||0|FS1800|pin@2||-3|0|pin@1||-1.5|0|ART_color()I74
AThicker|net@2||0|FS900|pin@6||-1.5|1|pin@7||-1.5|-1|ART_color()I74
AThicker|net@3||0|FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
AThicker|net@4||0|FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
AThicker|net@5||0|FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
AThicker|net@6||0|FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
Ed|D5G1;|pin@4||B
Eg|D5G1;|pin@3||I
Es|D5G1;|pin@0||B
X

# Cell NMOSf{sch}
CNMOSf;1{sch}|schematic|1021415734000|1098393023000||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5G1;HNPX-9;Y-13.5;)I2|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SM$(node_name) $(d) $(g) $(s) gnd N W='$(W)' L='$(L)' AD='2*$(W)*hdifn/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifn/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifn/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifn/0.1u)/($(source_shared)+1)'|ATTR_W(D5G1;HNPX-8.5;Y-12.5;)I3|ATTR_drain_shared(D5G1;HNPX-9;Y-16.5;)I0|ATTR_source_shared(D5G1;HNPX-9;Y-18;)I0|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
INMOSf;1{ic}|NMOSf@0||26.5|8.5||E|D0G4;|ATTR_Delay(D5G1;NTX3.5;Y-2;)I100|ATTR_L(D5G1;NTX3.5;)I2|ATTR_W(D6G1;NTX2;Y1;)I3|ATTR_drain_shared(D5G1;X0.5;Y2.5;)I0|ATTR_source_shared(D5G1;X0.5;Y-2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||6|-16.5|4|2||
NOff-Page|conn@1||6.5|0|4|2||
NOff-Page|conn@2||-16.5|-8|4|2||
NGround|gnd@0||5|-11|3|4||
N4-Port-Transistor|nmos4p@0||-2|-8|4|4|R||ATTR_length(D5G1;OJ)S"P(\"L\")"|ATTR_width(D5G1.5;OJX0.5;Y-1;)S"P(\"W\")"
NWire_Pin|pin@0||0|-16.5|0.5|0.5||
NWire_Pin|pin@1||0|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@2||-6.5|11|0|0|||ART_message(D5G6;)S[NMOSf]
Awire|net@0||0|0|conn@1|a|4.5|0|pin@1||0|0
Awire|net@1||0|0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
Awire|net@2||0|900|nmos4p@0|s|0|-10|pin@0||0|-16.5
Awire|net@3||0|1800|pin@0||0|-16.5|conn@0|a|4|-16.5
Awire|net@4||0|900|pin@1||0|0|nmos4p@0|d|0|-6
Awire|net@5||0|1800|nmos4p@0|b|0|-9|gnd@0||5|-9
Ed|D5G2;|conn@1|y|B
Eg|D5G2;|conn@2|a|I
Es|D5G2;|conn@0|y|B
X

# Cell NMOSfwk{ic}
CNMOSfwk;1{ic}|artwork|1021415734000|1047945058000|E|prototype_center()I[0,-8000]
Ngeneric:Facet-Center|art@0||0|0|0|0|R|AV
Ngeneric:Invisible-Pin|pin@0||-0.5|0|0|0|||ART_message(D5G1;)S[wk]
Ngeneric:Invisible-Pin|pin@1||0|-2|0|0||
NPin|pin@2||-1.25|0|1|1|RR|W
NPin|pin@3||-3|0|0|0|RR|W
Nschematic:Bus_Pin|pin@4||-3|0|0|0||
Nschematic:Bus_Pin|pin@5||0|2|0|0||
NPin|pin@6||0|-2|0|0||W
NPin|pin@7||-1.25|0.75|1|1||W
NPin|pin@8||-1.25|-0.75|1|1||W
NPin|pin@9||0|-0.75|0|0||W
NPin|pin@10||-0.75|-0.75|1|1||W
NPin|pin@11||-0.75|0.75|1|1||W
NPin|pin@12||0|0.75|0|0||W
NPin|pin@13||0|2|0|0||W
AThicker|net@0||0|FS900|pin@11||-0.75|0.75|pin@10||-0.75|-0.75|ART_color()I74
AThicker|net@1||0|FS1800|pin@3||-3|0|pin@2||-1.25|0|ART_color()I74
AThicker|net@2||0|FS900|pin@7||-1.25|0.75|pin@8||-1.25|-0.75|ART_color()I74
AThicker|net@3||0|FS900|pin@9||0|-0.75|pin@6||0|-2|ART_color()I74
AThicker|net@4||0|FS1800|pin@10||-0.75|-0.75|pin@9||0|-0.75|ART_color()I74
AThicker|net@5||0|FS0|pin@12||0|0.75|pin@11||-0.75|0.75|ART_color()I74
AThicker|net@6||0|FS900|pin@13||0|2|pin@12||0|0.75|ART_color()I74
Ed|D5G1;|pin@5||B
Eg|D5G1;|pin@4||I
Es|D5G1;|pin@1||B
X

# Cell NMOSfwk{sch}
CNMOSfwk;1{sch}|schematic|1021415734000|1047947171000||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5G1;HNPX-9;Y-13.5;)I2|ATTR_SPICE_template(D5G1;NTX4;Y-24;)SM$(node_name) $(d) $(g) $(s) gnd N W='$(W)' L='$(L)' AD='2*$(W)*hdifn/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifn/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifn/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifn/0.1u)/($(source_shared)+1)'|ATTR_W(D5G1;HNPX-8.5;Y-12.5;)I3|ATTR_drain_shared(D5G1;HNPX-8.5;Y-16.25;)I0|ATTR_source_shared(D5G1;HNPX-8.5;Y-17.75;)I0|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Srtranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
INMOSfwk;1{ic}|NMOSfwk@0||17|-1||E|D0G4;|ATTR_Delay(D5G1;NTX3.5;Y-2;)I100|ATTR_L(D5G1;NTX3.5;)I2|ATTR_M(T)I1|ATTR_W(D6G1;NTX2;Y1;)I3|ATTR_drain_shared(D5G1;X0.5;Y2.5;)I0|ATTR_source_shared(D5G1;X0.5;Y-2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||6|-16.5|4|2||
NOff-Page|conn@1||4.5|0|4|2||
NOff-Page|conn@2||-10|-8|4|2||
NGround|gnd@0||5|-11|3|4||
N4-Port-Transistor|nmos4p@0||-2|-8|4|4|R||ATTR_length(D5G1;OJ)S"P(\"L\")"|ATTR_width(D5G1.5;OJX0.5;Y-1;)S"P(\"W\")"
NWire_Pin|pin@0||0|-16.5|0.5|0.5||
NWire_Pin|pin@1||0|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@2||0|8.5|0|0|||ART_message(D5G6;)S[NMOSfwk]
Awire|net@0||0|900|nmos4p@0|s|0|-10|pin@0||0|-16.5
Awire|net@1||0|1800|pin@0||0|-16.5|conn@0|a|4|-16.5
Awire|net@2||0|1800|pin@1||0|0|conn@1|a|2.5|0
Awire|net@3||0|1800|conn@2|y|-8|-8|nmos4p@0|g|-3|-8
Awire|net@4||0|900|pin@1||0|0|nmos4p@0|d|0|-6
Awire|net@5||0|1800|nmos4p@0|b|0|-9|gnd@0||5|-9
Ed|D5G2;|conn@1|y|B
Eg|D5G2;|conn@2|a|I
Es|D5G2;|conn@0|y|B
X

# Cell PMOS4f{ic}
CPMOS4f;1{ic}|artwork|1021415734000|1085594334000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-2|0|1|1|||ART_color()I74
NPin|pin@0||-0.5|0.25|1|1|YRR|W
NPin|pin@1||-0.5|0.75|1|1|YRR|W
NPin|pin@2||-0.75|0.5|1|1|Y|W
NPin|pin@3||0|0.5|0|0||W
Ngeneric:Invisible-Pin|pin@4||0|2|0|0||
Ngeneric:Invisible-Pin|pin@5||0|0.5|0|0||
Nschematic:Bus_Pin|pin@6||0|-2|0|0||
Nschematic:Bus_Pin|pin@7||-3|0|0|0||
NPin|pin@8||0|1|0|0||W
NPin|pin@9||-0.75|1|1|1||W
NPin|pin@10||-0.75|-1|1|1||W
NPin|pin@11||0|-1|0|0||W
NPin|pin@12||0|-2|0|0||W
NPin|pin@13||-3|0|0|0|RR|W
NPin|pin@14||-2.5|0|1|1|RR|W
NPin|pin@15||0|2|0|0||W
NPin|pin@16||-1.5|-1|1|1||W
NPin|pin@17||-1.5|1|1|1||W
AThicker|net@0||0|FS3150|pin@0||-0.5|0.25|pin@2||-0.75|0.5|ART_color()I74
AThicker|net@1||0|FS450|pin@1||-0.5|0.75|pin@2||-0.75|0.5|ART_color()I74
AThicker|net@2||0|FS0|pin@3||0|0.5|pin@2||-0.75|0.5|ART_color()I74
AThicker|net@3||0|FS0|pin@8||0|1|pin@9||-0.75|1|ART_color()I74
AThicker|net@4||0|FS1800|pin@10||-0.75|-1|pin@11||0|-1|ART_color()I74
AThicker|net@5||0|FS1800|pin@13||-3|0|pin@14||-2.5|0|ART_color()I74
AThicker|net@6||0|FS2700|pin@8||0|1|pin@15||0|2|ART_color()I74
AThicker|net@7||0|FS900|pin@11||0|-1|pin@12||0|-2|ART_color()I74
AThicker|net@8||0|FS900|pin@9||-0.75|1|pin@10||-0.75|-1|ART_color()I74
AThicker|net@9||0|FS900|pin@17||-1.5|1|pin@16||-1.5|-1|ART_color()I74
Eb|D5G1;|pin@5||B
Ed|D5G1;|pin@6||B
Eg|D5G1;|pin@7||I
Es|D5G1;|pin@4||B
X

# Cell PMOS4f{sch}
CPMOS4f;1{sch}|schematic|1021415734000|1098423419000||ATTR_Delay(D5G1;HNPX-8.5;Y-1.25;)I100|ATTR_L(D5G1;HNPX-8.5;Y0.25;)I2|ATTR_SPICE_template(D5G1;NTX3.5;Y-9;)SM$(node_name) $(d) $(g) $(s) $(b) P W='$(W)' L='$(L)' AD='2*$(W)*hdifp/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifp/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifp/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifp/0.1u)/($(source_shared)+1)'|ATTR_W(D5G1;HNPX-8.75;Y2;)I3|ATTR_drain_shared(D5G1;HNPX-9;Y-3.25;)I0|ATTR_source_shared(D5G1;HNPX-9.5;Y-4.75;)I0|ATTR_verilog_template(D5G1;NTX1;Y-11;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
IPMOS4f;1{ic}|PMOS4f@0||20.75|16||E|D0G4;|ATTR_Delay(D5G1;NTX3.5;Y-2;)I100|ATTR_L(D5G1;NTX3.5;)I2|ATTR_W(D6G1;NTX2;Y1;)I3|ATTR_drain_shared(D5G1;X0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;X0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||5|11.5|4|2||
NOff-Page|conn@1||5|8|4|2||
NOff-Page|conn@2||-19|7|4|2||
NOff-Page|conn@3||5|1|4|2||
NWire_Pin|pin@0||0|11.5|0.5|0.5||
NWire_Pin|pin@1||0|1|0.5|0.5||
Ngeneric:Invisible-Pin|pin@2||-1|23|0|0|||ART_message(D5G6;)S[pmos4]
Ngeneric:Invisible-Pin|pin@3||-1.5|19.5|0|0|||ART_message(D5G2;)S[4 terminal PMOS device]
N4-Port-Transistor|pmos4p@0||-2|7|4|4|YR|2|ATTR_length(D5G1;OJX1.5;)S"P(\"L\")"|ATTR_width(D5G1.5;OJX-0.5;Y-2;)S"P(\"W\")"
Awire|net@0||0|0|pmos4p@0|g|-3|7|conn@2|y|-17|7
Awire|net@1||0|1800|pin@0||0|11.5|conn@0|a|3|11.5
Awire|net@2||0|2700|pmos4p@0|s|0|9|pin@0||0|11.5
Awire|net@3||0|1800|pmos4p@0|b|0|8|conn@1|a|3|8
Awire|net@4||0|0|conn@3|a|3|1|pin@1||0|1