purplegeneric180.jelib

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

Ngeneric:Invisible-Pin|pin@0||0|-0.12|0|0|||ART_message(D5G2;)S[Kp]
Nschematic:Bus_Pin|pin@1||-2.5|-1|0|0||
Nschematic:Bus_Pin|pin@2||-2.5|1|0|0||
Nschematic:Bus_Pin|pin@3||2.5|0|0|0||
NPin|pin@4||-1.5|-2|1|1||W
NPin|pin@5||-1.5|2|1|1||W
NPin|pin@6||-2.5|1|0|0||W
NPin|pin@7||-1.5|1|1|1||W
NPin|pin@8||1.5|0|1|1||W
NPin|pin@9||-1.5|-1|1|1||W
NPin|pin@10||-2.5|-1|0|0||W
AThicker|net@0||0|FS0|pin@7||-1.5|1|pin@6||-2.5|1|ART_color()I78
AThicker|net@1||0|FS3263|pin@8||1.5|0|pin@5||-1.5|2|ART_color()I78
AThicker|net@2||0|FS336|pin@8||1.5|0|pin@4||-1.5|-2|ART_color()I78
AThicker|net@3||0|FS0|pin@9||-1.5|-1|pin@10||-2.5|-1|ART_color()I78
AThicker|net@4||0|FS2700|pin@4||-1.5|-2|pin@5||-1.5|2|ART_color()I78
Ein[n]|D5G1;|pin@1||I
Ein[p]|D5G1;|pin@2||I
Eout|D5G1;|pin@3||O
X

# Cell inv2iKp{sch}
Cinv2iKp;1{sch}|schematic|1021415734000|1084951876000||ATTR_Delay(D5G1;HNPX-13.5;Y-8;)I100|ATTR_LEGATE(D5G1;HNPTX-13.5;Y-13;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-13.5;Y-9;)I-1|ATTR_X(D5G1;HNOJPX-13.5;Y-7;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-13.5;Y-11;)Sstrong0|ATTR_drive1(D5G1;HNPTX-13.5;Y-12;)Sstrong1|ATTR_su(D5G1;HNPTX-13.5;Y-10;)I-1|prototype_center()I[0,0]
IredGeneric180:NMOSwk;1{ic}|NMOSwk@0||4.5|5.5||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/10.
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||-10.5|-1|4|2|Y|
NOff-Page|conn@1||-10.5|1|4|2|Y|
NOff-Page|conn@2||15|0|4|2||
NGround|gnd@0||4.5|11|3|3|Y|
IredGeneric180:inv2i;1{ic}|inv2i@0||0|0||E|D0G4;|ATTR_Delay(D5G1;NOJPX2;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X|ATTR_drive0(OJP)S@drive0|ATTR_drive1(OJP)S@drive1
Iinv2iKp;1{ic}|inv2iKp@0||28|12||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-2;)I100|ATTR_LEGATE(PT)I1|ATTR_LEPARALLGRP(PT)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(PT)I-1
Ngeneric:Invisible-Pin|pin@0||24.5|0|0|0|||VERILOG_code(D6G1;)S[initial begin,	force out = 0;,	#30000 release out;,end]
NWire_Pin|pin@1||-4.5|1|0.5|0.5||
Ngeneric:Invisible-Pin|pin@2||23.5|5.5|0|0|||SIM_spice_card(D6G1;)S[.ic v(out) 'vlo']
Ngeneric:Invisible-Pin|pin@3||0|19|0|0|||ART_message(D5G2;)S[two-input inverter with p-side keeper]
Ngeneric:Invisible-Pin|pin@4||0|24|0|0|||ART_message(D5G6;)S[inv2iKp]
Ngeneric:Invisible-Pin|pin@5||0|17|0|0|||ART_message(D5G2;)S[P to N width ratio is 2 to 1]
Ngeneric:Invisible-Pin|pin@6||21.5|-8|0|0|||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
NWire_Pin|pin@7||4.5|0|0.5|0.5||
NWire_Pin|pin@8||-4.5|5.5|0.5|0.5||
Awire|net@0||0|1800|conn@0|y|-8.5|-1|inv2i@0|in[n]|-2.5|-1
Awire|net@1||0|1800|pin@1||-4.5|1|inv2i@0|in[p]|-2.5|1
Awire|net@2||0|1800|inv2i@0|out|2.5|0|pin@7||4.5|0
Awire|net@3||0|2700|pin@7||4.5|0|NMOSwk@0|s|4.5|3.5
Awire|net@4||0|2700|NMOSwk@0|d|4.5|7.5|gnd@0||4.5|9.5
Awire|net@5||0|1800|pin@8||-4.5|5.5|NMOSwk@0|g|1.5|5.5
Awire|net@6||0|2700|pin@1||-4.5|1|pin@8||-4.5|5.5
Awire|net@7||0|1800|conn@1|y|-8.5|1|pin@1||-4.5|1
Awire|net@8||0|0|conn@2|a|13|0|pin@7||4.5|0
Ein[n]|D5G2;|conn@0|a|I|ATTR_le(D5G1;NY2;)F0.33
Ein[p]|D5G2;|conn@1|a|I|ATTR_le(D5G1;NY-2;)F0.67
Eout|D5G2;|conn@2|y|O|ATTR_diffn(D5G1;NY-2.5;)I1|ATTR_diffp(D5G1;NY-1.5;)I2|ATTR_le(D5G1;NX-0.5;Y2;)I1
X

# Cell inv2iKpD{ic}
Cinv2iKpD;1{ic}|artwork|1021415734000|1061318580000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||2|0|1|1|||ART_color()I78
NThick-Circle|art@2||-1|1|1|1|||ART_color()I78
NThick-Circle|art@3||0|1.5|1|1|||ART_color()I78
NPin|pin@0||-2.5|-1|0|0||W
NPin|pin@1||-1.5|-1|1|1||W
NPin|pin@2||1.5|0|1|1||W
NPin|pin@3||-1.5|1|1|1||W
NPin|pin@4||-2.5|1|0|0||W
NPin|pin@5||-1.5|2|1|1||W
NPin|pin@6||-1.5|-2|1|1||W
Nschematic:Bus_Pin|pin@7||2.5|0|0|0||
Nschematic:Bus_Pin|pin@8||-2.5|1|0|0||
Nschematic:Bus_Pin|pin@9||-2.5|-1|0|0||
Ngeneric:Invisible-Pin|pin@10||0|-0.12|0|0|||ART_message(D5G2;)S[Kp]
Ngeneric:Invisible-Pin|pin@11||0|2|0|0||
AThicker|net@0||0|FS2700|pin@6||-1.5|-2|pin@5||-1.5|2|ART_color()I78
AThicker|net@1||0|FS0|pin@1||-1.5|-1|pin@0||-2.5|-1|ART_color()I78
AThicker|net@2||0|FS336|pin@2||1.5|0|pin@6||-1.5|-2|ART_color()I78
AThicker|net@3||0|FS3263|pin@2||1.5|0|pin@5||-1.5|2|ART_color()I78
AThicker|net@4||0|FS0|pin@3||-1.5|1|pin@4||-2.5|1|ART_color()I78
Ectl|D5G2;|pin@11||I
Ein[n]|D5G1;|pin@9||I
Ein[p]|D5G1;|pin@8||I
Eout|D5G1;|pin@7||O
X

# Cell inv2iKpD{sch}
Cinv2iKpD;1{sch}|schematic|1021415734000|1084951876000||ATTR_Delay(D5G1;HNPX-13.5;Y-8;)I100|ATTR_LEGATE(D5G1;HNPTX-13.5;Y-13;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-13.5;Y-9;)I-1|ATTR_X(D5G1;HNOJPX-13.5;Y-7;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-13.5;Y-11;)Sstrong0|ATTR_drive1(D5G1;HNPTX-13.5;Y-12;)Sstrong1|ATTR_su(D5G1;HNPTX-13.5;Y-10;)I-1|prototype_center()I[0,0]
IredGeneric180:NMOSwk;1{ic}|NMOSwk@0||4.5|5.5||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/10.
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||15|0|4|2||
NOff-Page|conn@1||-10.5|1|4|2|Y|
NOff-Page|conn@2||-10.5|-1|4|2|Y|
NOff-Page|conn@3||-4|-6|4|2||
NGround|gnd@0||4.5|11|3|3|Y|
IredGeneric180:inv2iCTLp;1{ic}|inv2iCTL@0||0|0||E|D0G4;|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X
Iinv2iKpD;1{ic}|inv2iKpD@0||28|12||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-2;)I100|ATTR_LEGATE(PT)I1|ATTR_LEPARALLGRP(PT)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(PT)I-1
Ngeneric:Invisible-Pin|pin@0||1|14|0|0|||ART_message(D5G2;)S["set input is P, reset input is N"]
NWire_Pin|pin@1||-4.5|5.5|0.5|0.5||
NWire_Pin|pin@2||4.5|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@3||21.5|-8|0|0|||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
Ngeneric:Invisible-Pin|pin@4||0|17|0|0|||ART_message(D5G2;)S[P to N width ratio is 2 to 1]
Ngeneric:Invisible-Pin|pin@5||0|24|0|0|||ART_message(D5G6;)S[inv2iKpD]
Ngeneric:Invisible-Pin|pin@6||0|19|0|0|||ART_message(D5G2;)S[degradable two-input inverter with p-side keeper]
Ngeneric:Invisible-Pin|pin@7||23.5|5.5|0|0|||SIM_spice_card(D6G1;)S[.ic v(out) 'vlo']
NWire_Pin|pin@8||-4.5|1|0.5|0.5||
Ngeneric:Invisible-Pin|pin@9||24.5|0|0|0|||VERILOG_code(D6G1;)S[initial begin,	force out = 0;,	#30000 release out;,end]
NWire_Pin|pin@10||0|-6|0.5|0.5||
Awire|net@0||0|2700|pin@2||4.5|0|NMOSwk@0|s|4.5|3.5
Awire|net@1||0|2700|NMOSwk@0|d|4.5|7.5|gnd@0||4.5|9.5
Awire|net@2||0|1800|pin@1||-4.5|5.5|NMOSwk@0|g|1.5|5.5
Awire|net@3||0|1800|pin@8||-4.5|1|inv2iCTL@0|inP|-2.5|1
Awire|net@4||0|900|inv2iCTL@0|ctl|0|-2|pin@10||0|-6
Awire|net@5||0|1800|inv2iCTL@0|out|2.5|0|pin@2||4.5|0
Awire|net@6||0|1800|conn@2|y|-8.5|-1|inv2iCTL@0|inN|-2.5|-1
Awire|net@7||0|0|conn@0|a|13|0|pin@2||4.5|0
Awire|net@8||0|1800|conn@1|y|-8.5|1|pin@8||-4.5|1
Awire|net@9||0|2700|pin@8||-4.5|1|pin@1||-4.5|5.5
Awire|net@10||0|0|pin@10||0|-6|conn@3|y|-2|-6
Ectl|D4G2;|conn@3|a|I|ATTR_le(D5G1;NX1;Y-2;)F1.33
Ein[n]|D5G2;|conn@2|a|I|ATTR_le(D5G1;NY2;)F0.33
Ein[p]|D5G2;|conn@1|a|I|ATTR_le(D5G1;NY-2;)F1.33
Eout|D5G2;|conn@0|y|O|ATTR_diffn(D5G1;NY-2.5;)I1|ATTR_diffp(D5G1;NY-1.5;)I4
X

# Cell inv2iLT{ic}
Cinv2iLT;2{ic}|artwork|1021415734000|1023396698000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOpened-Thicker-Polygon|art@1||-0.25|0|0.5|1|||ART_color()I78|trace()V[-0.25/0.5,-0.25/-0.5,0.25/-0.5]
NThick-Circle|art@2||-1|1|1|1|||ART_color()I78
NThick-Circle|art@3||2|0|1|1|||ART_color()I78
NPin|pin@0||-2.5|-1|0|0||W
NPin|pin@1||-1.5|-1|1|1||W
NPin|pin@2||1.5|0|1|1||W
NPin|pin@3||-1.5|1|1|1||W
NPin|pin@4||-2.5|1|0|0||W
NPin|pin@5||-1.5|2|1|1||W
NPin|pin@6||-1.5|-2|1|1||W
Nschematic:Bus_Pin|pin@7||-2.5|-1|0|0||
Nschematic:Bus_Pin|pin@8||-2.5|1|0|0||
Nschematic:Bus_Pin|pin@9||2.5|0|0|0||
AThicker|net@0||0|FS0|pin@1||-1.5|-1|pin@0||-2.5|-1|ART_color()I78
AThicker|net@1||0|FS2700|pin@6||-1.5|-2|pin@5||-1.5|2|ART_color()I78
AThicker|net@2||0|FS336|pin@2||1.5|0|pin@6||-1.5|-2|ART_color()I78
AThicker|net@3||0|FS3263|pin@2||1.5|0|pin@5||-1.5|2|ART_color()I78
AThicker|net@4||0|FS0|pin@3||-1.5|1|pin@4||-2.5|1|ART_color()I78
Ein[n]|D5G1;|pin@7||I
Ein[p]|D5G1;|pin@8||I
Eout|D5G1;|pin@9||O
X

# Cell inv2iLT{sch}
Cinv2iLT;2{sch}|schematic|1021415734000|1084951876000||ATTR_Delay(D5G1;HNPX-11.5;Y-8.5;)I100|ATTR_LEGATE(D5G1;HNPTX-11.5;Y-13.5;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-12;Y-9.5;)I-1|ATTR_X(D5G1;HNOJPX-11.5;Y-7.5;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-11.5;Y-11.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-11.5;Y-12.5;)Sstrong1|ATTR_su(D5G1;HNPTX-11.5;Y-10.5;)I-1|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||-10|-1|4|2|Y|
NOff-Page|conn@1||-10|1|4|2|Y|
NOff-Page|conn@2||12.5|0|4|2||
IredGeneric180:inv2iLT;1{ic}|inv2iLT@0||0|0||E|D0G4;|ATTR_Delay(D5G1;NOJPX2;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X|ATTR_drive0(OJP)S@drive0|ATTR_drive1(OJP)S@drive1
Iinv2iLT;2{ic}|inv2iLT@1||21|10||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-2;)I100|ATTR_LEGATE(PT)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(PT)I-1
Ngeneric:Invisible-Pin|pin@0||16|-12.5|0|0|||ART_message(D5G2;)S[X is drive strength,N drive strength is twice P strength]
Ngeneric:Invisible-Pin|pin@1||0.5|11.5|0|0|||ART_message(D5G2;)S[P to N width ratio is 2 to 2]
Ngeneric:Invisible-Pin|pin@2||-3.5|16|0|0|||ART_message(D5G2;)S[two-input LO-threshold inverter]
Ngeneric:Invisible-Pin|pin@3||0.5|18.5|0|0|||ART_message(D5G6;)S[inv2iLT]
Awire|net@0||0|0|inv2iLT@0|in[n]|-2.5|-1|conn@0|y|-8|-1
Awire|net@1||0|0|inv2iLT@0|in[p]|-2.5|1|conn@1|y|-8|1
Awire|net@2||0|0|conn@2|a|10.5|0|inv2iLT@0|out|2.5|0
Ein[n]|D5G2;|conn@0|a|I|ATTR_le(D5G1;NY2.5;)F0.67
Ein[p]|D5G2;|conn@1|a|I|ATTR_le(D5G1;NY-2;)F0.67
Eout|D5G2;|conn@2|y|O|ATTR_diffn(D5G1;NY-3;)I2|ATTR_diffp(D5G1;NY-2;)I2|ATTR_le(D5G1;NY2;)F1.33
X

# Cell inv2o{ic}
Cinv2o;1{ic}|artwork|1021415734000|1016226050000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOpened-Thicker-Polygon|art@1||-0.5|-1|0.5|1|||ART_color()I78|trace()V[-0.25/0.5,-0.25/-0.5,0.25/-0.5]
NOpened-Thicker-Polygon|art@2||-0.5|1|0.5|1|||ART_color()I78|trace()V[-0.25/-0.5,-0.25/0.5,-0.25/0,0.25/0,0.25/0.5,0.25/-0.5]
NThick-Circle|art@3||1|1|1|1|1200||ART_color()I78|ART_degrees()F[0.0,2.0943952]
NThick-Circle|art@4||2|-1|1|1|||ART_color()I78
NThick-Circle|art@5||2|1|1|1|||ART_color()I78
NPin|pin@0||1.5|-1|1|1||W
NPin|pin@1||0|0|1|1||W
NPin|pin@2||-1.5|-3|1|1||W
NPin|pin@3||1.5|1|1|1||W
NPin|pin@4||-1.5|3|1|1||W
NPin|pin@5||0|0|1|1||W
NPin|pin@6||-2.5|0|1|1||W
NPin|pin@7||-1.5|0|1|1||W
Nschematic:Wire_Pin|pin@8||2.5|-1|0|0||
Nschematic:Bus_Pin|pin@9||-2.5|0|0|0||
Nschematic:Bus_Pin|pin@10||2.5|1|0|0||
AThicker|net@0||0|FS2700|pin@2||-1.5|-3|pin@4||-1.5|3|ART_color()I78
AThicker|net@1||0|FS336|pin@0||1.5|-1|pin@2||-1.5|-3|ART_color()I78
AThicker|net@2||0|FS3263|pin@0||1.5|-1|pin@1||0|0|ART_color()I78
AThicker|net@3||0|FS336|pin@3||1.5|1|pin@5||0|0|ART_color()I78
AThicker|net@4||0|FS3263|pin@3||1.5|1|pin@4||-1.5|3|ART_color()I78
AThicker|net@5||0|FS0|pin@7||-1.5|0|pin@6||-2.5|0|ART_color()I78
Ein|D5G1;|pin@9||I
Eout[n]|D5G1;|pin@8||O
Eout[p]|D5G1;HN|pin@10||O
X

# Cell inv2o{sch}
Cinv2o;1{sch}|schematic|1021415734000|1084380427000||ATTR_X(D5G1;HNOJPX-18;Y-3.5;)S"LE.subdrive(\"invHT1\", \"X\")"|ATTR_delayH(D5G1;HNPX-18;Y-5.5;)I100|ATTR_delayL(D5G1;HNPX-18;Y-6.5;)I100|ATTR_su(D5G1;HNPTX-18;Y-4.5;)I-1|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||16|-2|4|2||
NOff-Page|conn@1||-16|0|4|2||