purplegeneric180.jelib

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

IredGeneric180:inv2iHT;1{ic}|inv2iHT@0||0|0||E|D0G4;|ATTR_Delay(D5G1;NOJPX2;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X|ATTR_drive0(OJP)S@drive0|ATTR_drive1(OJP)S@drive1
Iinv2iHT;1{ic}|inv2iHT@1||23|12.5||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-2;)I100|ATTR_LEGATE(PT)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(PT)I-1
Ngeneric:Invisible-Pin|pin@0||13|-11|0|0|||ART_message(D5G2;)S[X is drive strength,P drive strength is twice N strength]
Ngeneric:Invisible-Pin|pin@1||-3.5|13.5|0|0|||ART_message(D5G2;)S[P to N width ratio is 4 to 1]
Ngeneric:Invisible-Pin|pin@2||-3.5|20.5|0|0|||ART_message(D5G6;)S[inv2iHT]
Ngeneric:Invisible-Pin|pin@3||-3.5|15.5|0|0|||ART_message(D5G2;)S[two-input HI-threshold inverter]
Awire|net@0||0|0|inv2iHT@0|in[p]|-2.5|1|conn@1|y|-8|1
Awire|net@1||0|0|inv2iHT@0|in[n]|-2.5|-1|conn@2|y|-8|-1
Awire|net@2||0|0|conn@0|a|10|0|inv2iHT@0|out|2.5|0
Ein[n]|D5G2;|conn@2|a|I|ATTR_le(D5G1;NX0.5;Y2;)F0.33
Ein[p]|D5G2;|conn@1|a|I|ATTR_le(D5G1;NY-1.5;)F1.33
Eout|D5G2;|conn@0|y|O|ATTR_diffn(D5G1;NY-2.5;)I1|ATTR_diffp(D5G1;NY-1.5;)I4|ATTR_le(D5G1;NY2;)F1.67
X

# Cell inv2iK{ic}
Cinv2iK;1{ic}|artwork|1021415734000|1058220438000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-1|1|1|1|||ART_color()I78
NThick-Circle|art@2||2|0|1|1|||ART_color()I78
Ngeneric:Invisible-Pin|pin@0||0|-0.12|0|0|||ART_message(D5G2;)S[K]
Nschematic:Bus_Pin|pin@1||-2.5|-1|0|0||
Nschematic:Bus_Pin|pin@2||-2.5|1|0|0||
Nschematic:Bus_Pin|pin@3||2.5|0|0|0||
NPin|pin@4||-1.5|-2|1|1||W
NPin|pin@5||-1.5|2|1|1||W
NPin|pin@6||-2.5|1|0|0||W
NPin|pin@7||-1.5|1|1|1||W
NPin|pin@8||1.5|0|1|1||W
NPin|pin@9||-1.5|-1|1|1||W
NPin|pin@10||-2.5|-1|0|0||W
AThicker|net@0||0|FS0|pin@7||-1.5|1|pin@6||-2.5|1|ART_color()I78
AThicker|net@1||0|FS3263|pin@8||1.5|0|pin@5||-1.5|2|ART_color()I78
AThicker|net@2||0|FS336|pin@8||1.5|0|pin@4||-1.5|-2|ART_color()I78
AThicker|net@3||0|FS0|pin@9||-1.5|-1|pin@10||-2.5|-1|ART_color()I78
AThicker|net@4||0|FS2700|pin@4||-1.5|-2|pin@5||-1.5|2|ART_color()I78
Ein[n]|D5G1;|pin@1||I
Ein[p]|D5G1;|pin@2||I
Eout|D5G1;|pin@3||O
X

# Cell inv2iK{sch}
Cinv2iK;1{sch}|schematic|1021415734000|1084951876000||ATTR_Delay(D5G1;HNPX-13.5;Y-8;)I100|ATTR_LEGATE(D5G1;HNPTX-13.5;Y-13;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-13.5;Y-9;)I-1|ATTR_X(D5G1;HNOJPX-13.5;Y-7;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-13.5;Y-11;)Sstrong0|ATTR_drive1(D5G1;HNPTX-13.5;Y-12;)Sstrong1|ATTR_su(D5G1;HNPTX-13.5;Y-10;)I-1|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||-10.5|-1|4|2|Y|
NOff-Page|conn@1||-10.5|1|4|2|Y|
NOff-Page|conn@2||24|0|4|2||
IredGeneric180:inv2i;1{ic}|inv2i@0||0|0||E|D0G4;|ATTR_Delay(D5G1;NOJPX2;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X|ATTR_drive0(OJP)S@drive0|ATTR_drive1(OJP)S@drive1
Iinv2iK;1{ic}|inv2iK@0||24|17||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-2;)I100|ATTR_LEGATE(PT)I1|ATTR_LEPARALLGRP(PT)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(PT)I-1
IredGeneric180:invK;1{ic}|invK@0||8|6|R|E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X/20.|ATTR_drive0(P)Sweak0|ATTR_drive1(P)Sweak1
IredGeneric180:invK;1{ic}|invK@1||14.5|6|YR|E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X/20.|ATTR_drive0(P)Sweak0|ATTR_drive1(P)Sweak1
NWire_Pin|pin@0||8|10.5|0.5|0.5||
NWire_Pin|pin@1||14.5|10.5|0.5|0.5||
NWire_Pin|pin@2||14.5|0|0.5|0.5||
NWire_Pin|pin@3||8|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@4||11|-5|0|0|||SIM_spice_card(D6G1;)S[.ic v(out) 'vhi']
Ngeneric:Invisible-Pin|pin@5||-4|20|0|0|||ART_message(D5G2;)S[two-input inverter with keeper]
Ngeneric:Invisible-Pin|pin@6||-4|25|0|0|||ART_message(D5G6;)S[inv2iK]
Ngeneric:Invisible-Pin|pin@7||-4|18|0|0|||ART_message(D5G2;)S[P to N width ratio is 2 to 1]
Ngeneric:Invisible-Pin|pin@8||14.5|-12.5|0|0|||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
Awire|net@0||0|1800|conn@0|y|-8.5|-1|inv2i@0|in[n]|-2.5|-1
Awire|net@1||0|1800|conn@1|y|-8.5|1|inv2i@0|in[p]|-2.5|1
Awire|net@2||0|1800|inv2i@0|out|2.5|0|pin@3||8|0
Awire|net@3||0|2700|pin@3||8|0|invK@0|in|8|3.5
Awire|net@4||0|2700|invK@0|out|8|8.5|pin@0||8|10.5
Awire|net@5||0|900|pin@1||14.5|10.5|invK@1|in|14.5|8.5
Awire|net@6||0|2700|pin@2||14.5|0|invK@1|out|14.5|3.5
Awire|net@7||0|1800|pin@0||8|10.5|pin@1||14.5|10.5
Awire|net@8||0|1800|pin@3||8|0|pin@2||14.5|0
Awire|net@9||0|1800|pin@2||14.5|0|conn@2|a|22|0
Ein[n]|D5G2;|conn@0|a|I|ATTR_le(D5G1;NY2;)F0.33
Ein[p]|D5G2;|conn@1|a|I|ATTR_le(D5G1;NY-2;)F0.67
Eout|D5G2;|conn@2|y|O|ATTR_diffn(D5G1;NY-2.5;)I1|ATTR_diffp(D5G1;NY-1.5;)I2
X

# Cell inv2iKn{ic}
Cinv2iKn;1{ic}|artwork|1021415734000|1058220438000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||2|0|1|1|||ART_color()I78
NThick-Circle|art@2||-1|1|1|1|||ART_color()I78
NPin|pin@0||-2.5|-1|0|0||W
NPin|pin@1||-1.5|-1|1|1||W
NPin|pin@2||1.5|0|1|1||W
NPin|pin@3||-1.5|1|1|1||W
NPin|pin@4||-2.5|1|0|0||W
NPin|pin@5||-1.5|2|1|1||W
NPin|pin@6||-1.5|-2|1|1||W
Nschematic:Bus_Pin|pin@7||2.5|0|0|0||
Nschematic:Bus_Pin|pin@8||-2.5|1|0|0||
Nschematic:Bus_Pin|pin@9||-2.5|-1|0|0||
Ngeneric:Invisible-Pin|pin@10||0|-0.12|0|0|||ART_message(D5G2;)S[Kn]
AThicker|net@0||0|FS2700|pin@6||-1.5|-2|pin@5||-1.5|2|ART_color()I78
AThicker|net@1||0|FS0|pin@1||-1.5|-1|pin@0||-2.5|-1|ART_color()I78
AThicker|net@2||0|FS336|pin@2||1.5|0|pin@6||-1.5|-2|ART_color()I78
AThicker|net@3||0|FS3263|pin@2||1.5|0|pin@5||-1.5|2|ART_color()I78
AThicker|net@4||0|FS0|pin@3||-1.5|1|pin@4||-2.5|1|ART_color()I78
Ein[n]|D5G1;|pin@9||I
Ein[p]|D5G1;|pin@8||I
Eout|D5G1;|pin@7||O
X

# Cell inv2iKn{sch}
Cinv2iKn;1{sch}|schematic|1021415734000|1084951876000||ATTR_Delay(D5G1;HNPX-13.5;Y-8;)I100|ATTR_LEGATE(D5G1;HNPTX-13.5;Y-13;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-13.5;Y-9;)I-1|ATTR_X(D5G1;HNOJPX-13.5;Y-7;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-13.5;Y-11;)Sstrong0|ATTR_drive1(D5G1;HNPTX-13.5;Y-12;)Sstrong1|ATTR_su(D5G1;HNPTX-13.5;Y-10;)I-1|prototype_center()I[0,0]
IredGeneric180:PMOSwk;1{ic}|PMOSwk@0||4.5|-5.5||E|D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/20.
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||15|0|4|2||
NOff-Page|conn@1||-10.5|1|4|2|Y|
NOff-Page|conn@2||-10.5|-1|4|2|Y|
IredGeneric180:inv2i;1{ic}|inv2i@0||0|0||E|D0G4;|ATTR_Delay(D5G1;NOJPX2;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X|ATTR_drive0(OJP)S@drive0|ATTR_drive1(OJP)S@drive1
Iinv2iKn;1{ic}|inv2iKn@0||28|12||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-2;)I100|ATTR_LEGATE(PT)I1|ATTR_LEPARALLGRP(PT)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(PT)I-1
Ngeneric:Invisible-Pin|pin@0||27|-1|0|0|||VERILOG_code(D6G1;)S[initial begin,	force out = 1;,	#30000 release out;,end]
NWire_Pin|pin@1||-4.5|-1|0.5|0.5||
NWire_Pin|pin@2||-4.5|-5.5|0.5|0.5||
NWire_Pin|pin@3||4.5|0|0.5|0.5||
Ngeneric:Invisible-Pin|pin@4||21.5|-14.5|0|0|||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
Ngeneric:Invisible-Pin|pin@5||0|13|0|0|||ART_message(D5G2;)S[P to N width ratio is 2 to 1]
Ngeneric:Invisible-Pin|pin@6||0|20|0|0|||ART_message(D5G6;)S[inv2iKn]
Ngeneric:Invisible-Pin|pin@7||0|15|0|0|||ART_message(D5G2;)S[two-input inverter with n-side keeper]
Ngeneric:Invisible-Pin|pin@8||26.5|3|0|0|||SIM_spice_card(D6G1;)S[.ic v(out) 'vhi']
NPower|pwr@0||4.5|-10.5|3|3||
Awire|net@0||0|1800|pin@1||-4.5|-1|inv2i@0|in[n]|-2.5|-1
Awire|net@1||0|1800|conn@1|y|-8.5|1|inv2i@0|in[p]|-2.5|1
Awire|net@2||0|1800|inv2i@0|out|2.5|0|pin@3||4.5|0
Awire|net@3||0|900|pin@3||4.5|0|PMOSwk@0|s|4.5|-3.5
Awire|net@4||0|1800|pin@2||-4.5|-5.5|PMOSwk@0|g|1.5|-5.5
Awire|net@5||0|900|PMOSwk@0|d|4.5|-7.5|pwr@0||4.5|-10.5
Awire|net@6||0|0|conn@0|a|13|0|pin@3||4.5|0
Awire|net@7||0|900|pin@1||-4.5|-1|pin@2||-4.5|-5.5
Awire|net@8||0|1800|conn@2|y|-8.5|-1|pin@1||-4.5|-1
Ein[n]|D5G2;|conn@2|a|I|ATTR_le(D5G1;NY2;)F0.33
Ein[p]|D5G2;|conn@1|a|I|ATTR_le(D5G1;NY-2;)F0.67
Eout|D5G2;|conn@0|y|O|ATTR_diffn(D5G1;NY-2.5;)I1|ATTR_diffp(D5G1;NY-1.5;)I2|ATTR_le(D5G1;NY2;)I1
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# Cell inv2iKnD{ic}
Cinv2iKnD;1{ic}|artwork|1021415734000|1061319026000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-1|1|1|1|||ART_color()I78
NThick-Circle|art@2||2|0|1|1|||ART_color()I78
Ngeneric:Invisible-Pin|pin@0||0|-0.12|0|0|||ART_message(D5G2;)S[KnD]
Nschematic:Bus_Pin|pin@1||-2.5|-1|0|0||
Nschematic:Bus_Pin|pin@2||-2.5|1|0|0||
Nschematic:Bus_Pin|pin@3||2.5|0|0|0||
NPin|pin@4||-1.5|-2|1|1||W
NPin|pin@5||-1.5|2|1|1||W
NPin|pin@6||-2.5|1|0|0||W
NPin|pin@7||-1.5|1|1|1||W
NPin|pin@8||1.5|0|1|1||W
NPin|pin@9||-1.5|-1|1|1||W
NPin|pin@10||-2.5|-1|0|0||W
Ngeneric:Invisible-Pin|pin@11||0|2|0|0||
NPin|pin@12||0|1|0|0|R|W
NPin|pin@13||0|2|1|1|R|W
AThicker|net@0||0|FS0|pin@7||-1.5|1|pin@6||-2.5|1|ART_color()I78
AThicker|net@1||0|FS3263|pin@8||1.5|0|pin@5||-1.5|2|ART_color()I78
AThicker|net@2||0|FS336|pin@8||1.5|0|pin@4||-1.5|-2|ART_color()I78
AThicker|net@3||0|FS0|pin@9||-1.5|-1|pin@10||-2.5|-1|ART_color()I78
AThicker|net@4||0|FS2700|pin@4||-1.5|-2|pin@5||-1.5|2|ART_color()I78
AThicker|net@5||0|FS900|pin@13||0|2|pin@12||0|1|ART_color()I78
Ectl|D5G2;|pin@11||I
Ein[n]|D5G1;|pin@1||I
Ein[p]|D5G1;|pin@2||I
Eout|D5G1;|pin@3||O
X

# Cell inv2iKnD{sch}
Cinv2iKnD;1{sch}|schematic|1021415734000|1084951876000||ATTR_Delay(D5G1;HNPX-13.5;Y-8;)I100|ATTR_LEGATE(D5G1;HNPTX-13.5;Y-13;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-13.5;Y-9;)I-1|ATTR_X(D5G1;HNOJPX-13.5;Y-7;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-13.5;Y-11;)Sstrong0|ATTR_drive1(D5G1;HNPTX-13.5;Y-12;)Sstrong1|ATTR_su(D5G1;HNPTX-13.5;Y-10;)I-1|prototype_center()I[0,0]
IredGeneric180:PMOSwk;1{ic}|PMOSwk@0||4.5|-5.5||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/10.
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOff-Page|conn@0||-10.5|-1|4|2|Y|
NOff-Page|conn@1||-10.5|1|4|2|Y|
NOff-Page|conn@2||15|0|4|2||
NOff-Page|conn@3||-4|6|4|2||
IredGeneric180:inv2iCTLn;1{ic}|inv2iCTL@0||0|0||E|D0G4;|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X
Iinv2iKnD;1{ic}|inv2iKnD@0||28|12||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-2;)I100|ATTR_LEGATE(PT)I1|ATTR_LEPARALLGRP(PT)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(PT)I-1
Ngeneric:Invisible-Pin|pin@0||1|9|0|0|||ART_message(D5G2;)S["Set input in N, reset input is P"]
Ngeneric:Invisible-Pin|pin@1||26.5|3|0|0|||SIM_spice_card(D6G1;)S[.ic v(out) 'vhi']
Ngeneric:Invisible-Pin|pin@2||0|15|0|0|||ART_message(D5G2;)S[degradable two-input inverter with n-side keeper]
Ngeneric:Invisible-Pin|pin@3||0|20|0|0|||ART_message(D5G6;)S[inv2iKnD]
Ngeneric:Invisible-Pin|pin@4||0|13|0|0|||ART_message(D5G2;)S[P to N width ratio is 2 to 1]
Ngeneric:Invisible-Pin|pin@5||21.5|-14.5|0|0|||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
NWire_Pin|pin@6||4.5|0|0.5|0.5||
NWire_Pin|pin@7||-4.5|-5.5|0.5|0.5||
NWire_Pin|pin@8||-4.5|-1|0.5|0.5||
Ngeneric:Invisible-Pin|pin@9||27|-1|0|0|||VERILOG_code(D6G1;)S[initial begin,	force out = 1;,	#30000 release out;,end]
NWire_Pin|pin@10||0|6|0.5|0.5||
NPower|pwr@0||4.5|-10.5|3|3||
Awire|net@0||0|900|pin@6||4.5|0|PMOSwk@0|s|4.5|-3.5
Awire|net@1||0|1800|pin@7||-4.5|-5.5|PMOSwk@0|g|1.5|-5.5
Awire|net@2||0|900|PMOSwk@0|d|4.5|-7.5|pwr@0||4.5|-10.5
Awire|net@3||0|1800|conn@1|y|-8.5|1|inv2iCTL@0|inP|-2.5|1
Awire|net@4||0|2700|inv2iCTL@0|ctl|0|-2|pin@10||0|6
Awire|net@5||0|1800|inv2iCTL@0|out|2.5|0|pin@6||4.5|0
Awire|net@6||0|1800|pin@8||-4.5|-1|inv2iCTL@0|inN|-2.5|-1
Awire|net@7||0|1800|conn@0|y|-8.5|-1|pin@8||-4.5|-1
Awire|net@8||0|900|pin@8||-4.5|-1|pin@7||-4.5|-5.5
Awire|net@9||0|0|conn@2|a|13|0|pin@6||4.5|0
Awire|net@10||0|0|pin@10||0|6|conn@3|y|-2|6
Ectl|D4G2;|conn@3|a|I|ATTR_le(D5G1;NY-2;)F0.67
Ein[n]|D5G2;|conn@0|a|I|ATTR_le(D5G1;NY2;)F0.67
Ein[p]|D5G2;|conn@1|a|I|ATTR_le(D5G1;NY-2;)F0.67
Eout|D5G2;|conn@2|y|O|ATTR_diffn(D5G1;NY-2.5;)I2|ATTR_diffp(D5G1;NY-1.5;)I2
X

# Cell inv2iKp{ic}
Cinv2iKp;1{ic}|artwork|1021415734000|1058220438000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NThick-Circle|art@1||-1|1|1|1|||ART_color()I78
NThick-Circle|art@2||2|0|1|1|||ART_color()I78