purplegeneric180.jelib

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

Fina|-2.5|-2
Finb|-2.5|0
Finc|-2.5|2
Fout|2.5|0
Rnand3LTen_sy;1{ic}|-2.5|2.5|-3.5|3.5|1021415734000|1049318933000
Fina|-2.5|-2
Finb|-2.5|0
Finc|-2.5|2
Fout|2.5|0
Rnand3MLT;1{ic}|-2.5|2.5|-3.5|3.5|1021415734000|1048703082000
Fina|-2.5|-2
Finb|-2.5|0
Finc|-2.5|2
Fout|2.5|0
Rnand3en;1{ic}|-2.5|2.5|-3.5|3.5|1021415734000|1049309304000
Fina|-2.5|-2
Finb|-2.5|0
Finc|-2.5|2
Fout|2.5|0
Rnand3en_sy;1{ic}|-2.5|2.5|-3.5|3.5|1021415734000|1049312850000
Fina|-2.5|-2
Finb|-2.5|0
Finc|-2.5|2
Fout|2.5|0
Rnms2;1{ic}|-3|3|-3|6|1021415734000|1084377264000
Fd|0|6
Fg|-3|0
Fg2|3|4
Rnms2_sy;1{ic}|-3|3|-3|6|1021415734000|1084377287000
Fd|0|6
Fg|-3|0
Fg2|3|4
Rnms3;1{ic}|-3|3|-3|10|1021415734000|1084377312000
Fd|0|10
Fg|-3|0
Fg2|3|4
Fg3|-3|8
Rnms3_2sy;1{ic}|-4|3.5|-3|10|1021415734000|1049318895000
Fd|0|10
Fg|-2.25|0
Fg2|3|4
Fg3|-3|8
Rnms3_sy3;1{ic}|-3|12|-4|11|1021415734000|1048614173000
Fd|5|11
Fg|-3|0
Fg2|11.5|4
Fg3|-3|8
Rnor2;1{ic}|-2.5|2.5|-2.25|2|1021415734000|1079513648000
Fina|-2.5|-1
Finb|-2.5|1
Fout|2.5|0
Rnor2_sy;1{ic}|-2.5|2.5|-2|2|1021415734000|1055024971000
Fina|-2.5|-1
Finb|-2.5|1
Fout|2.5|0
Rnor2en;1{ic}|-2.5|2.5|-2.25|2|1021415734000|1080693625000
Fina|-2.5|-1
Finb|-2.5|1
Fout|2.5|0
Rnor2n;1{ic}|-2.5|2.5|-2.5|2.5|1021415734000|1052770339000
Fina|-2.5|-1
Finb|-2.5|1
Fout|2.5|0
RpassF;1{ic}|-3|3|-3|1.5|1094081205000|1094081925000
Fdrn|2|0
FpassF|0.5|-2
Fsrc|-2|0
RpassT;1{ic}|-3|3|-3|1.5|1094081205000|1094081753000
Fdrn|2|0
FpassT|-0.5|-2
Fsrc|-2|0
RpassTF;1{ic}|-3|3|-3|1.5|1094081205000|1094081421000
Fdrn|2|0
FpassF|0.5|-2
FpassT|-0.5|-2
Fsrc|-2|0
Rpms2;1{ic}|-3|3|-6|2.5|1021415734000|1084376993000
Fd|0|-6
Fg|-3|0
Fg2|3|-4
Rpms2_sy;1{ic}|-3|3|-6|2.5|1021415734000|1084377034000
Fd|0|-6
Fg|-3|0
Fg2|3|-4
Rpms3;1{ic}|-3.5|3|-10.25|2.5|1021415734000|1084377153000
Fd|0|-10
Fg|-3|0
Fg2|3|-4
Fg3|-3|-8
RtriInv;1{ic}|-3.5|3.5|-3|3|1092081409000|1092155957000
Fen|0|-2
FenB|0|2
Fin|-2.5|0
Fout|2.5|0
Rxor2;1{ic}|-3.5|1.53|-2.25|2|1021415734000|1085387251000
Fina|-3.5|-0.5
FinaB|-3.5|-1.5
Finb|-3.5|1.5
FinbB|-3.5|0.5
Fout|1.5|0

# Technologies:
Tartwork
Tgeneric
Tmocmos
Tschematic

# Cell LEsettings{ic}
CLEsettings;1{ic}|artwork|1023920563000|1025301943000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOpened-Thicker-Polygon|art@1||1.5|-0.5|9|9|||ART_color()I78|trace()V[-4.5/-3.5,-4.5/4.5,4.5/4.5,4.5/-4.5,-4.5/-4.5]
Ngeneric:Invisible-Pin|pin@0||1.5|4.5|0|0|||ART_message(D5G1;)S[LEsettings]
X

# Cell LEsettings{sch}
CLEsettings;1{sch}|schematic|1023920036000|1027355872000||ATTR_LESETTINGS(D6G1;HNPX-21;Y23;)I1|ATTR_SPICE_template(D5G1;NTX-7;Y9;)S**LEsettings: None needed for LEsettings|ATTR_diffn(D6G1;HNPX-21;Y25;)F0.7|ATTR_diffp(D6G1;HNPX-21;Y24;)F0.7|ATTR_epsilon(D6G1;HNPX-21;Y28;)F0.1|ATTR_gate_cap(D6G1;HNPX-21;Y26;)F0.4|ATTR_keeper_ratio(D5G1;HNPX-15.5;Y22;)F0.1|ATTR_max_iter(D6G1;HNPX-21;Y27;)I40|ATTR_su(D6G1;HNPX-21;Y30;)I4|ATTR_wire_ratio(D6G1;HNPX-21;Y29;)F0.16|prototype_center()I[0,0]
ILEsettings;1{ic}|LEsettin@0||-6|16.5||E|D0G4;|ATTR_LESETTINGS(D5G1;NPTX-4.25;Y-4;)I1|ATTR_diffn(D6G1;NPTX-4;Y-1.5;)F0.7|ATTR_diffp(D6G1;NPTX-4;Y-2.5;)F0.7|ATTR_epsilon(D6G1;NPTX-4;Y1.5;)F0.1|ATTR_gate_cap(D6G1;NPTX-4;Y-0.5;)F0.4|ATTR_keeper_ratio(D6G1;NPTX-4;Y-3.5;)F0.1|ATTR_max_iter(D6G1;NPTX-4;Y0.5;)I40|ATTR_su(D6G1;NPTX-4;Y3.5;)F3.7|ATTR_wire_ratio(D6G1;NPTX-4;Y2.5;)F0.16
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
Ngeneric:Invisible-Pin|pin@0||-9.5|12|0|0|||ART_message(D6G1;)S[this is the diffusion effort of PMOS gates (Cdiffp/Cgate)]
Ngeneric:Invisible-Pin|pin@1||-9.5|13|0|0|||ART_message(D6G1;)S[this is the diffusion effort of NMOS gates (Cdiffn/Cgate)]
Ngeneric:Invisible-Pin|pin@2||-9.5|14|0|0|||ART_message(D6G1;)S[gate cap. is used to convert cap loads to gate loads (fF/lambda)]
Ngeneric:Invisible-Pin|pin@3||-9.5|15|0|0|||ART_message(D6G1;)S[this sets the maximum number of iterations]
Ngeneric:Invisible-Pin|pin@4||-9.5|16|0|0|||ART_message(D6G1;)S[epsilon is the convergence criterion]
Ngeneric:Invisible-Pin|pin@5||-9.5|17|0|0|||ART_message(D6G1;)S[wire ratio is the default wire ratio: Cwire/Cgate]
Ngeneric:Invisible-Pin|pin@6||-9.5|18|0|0|||ART_message(D6G1;)S[su is the global step-up (fan-out)]
Ngeneric:Invisible-Pin|pin@7||-24|21|0|0|||ART_message(D6G2;)S[This Facet is used to set Logical Effort Settings]
X

# Cell aChangeRecord{doc}
CaChangeRecord;1{doc}|mocmos|1021415734000|1021421067000||FACET_message()S[This is a change record for the purpleOne library.,"",9 March 02,Ivan added alternate icons for four types of NAND gates.,Ivan fixed output port location on one of the NAND gates.,Ivan set the scale of the pass gate be normalized to minimum transistor.,Ivan checked that all internal expressions are in Java.,Making a new icon copies the form of the icon in the schematic but,    DOES NOT MAKE ITS PARAMETER BE Java type.,Ivan updated the dates on the libraries to 9 March 2002,"",14 Apr 2002,"JKG: Minor fixes on text, etc","",14 May 2002,"JKG: Added nmos, nmos4, pmos, pmos4 primitives to allow Monte Carlo simulations","JKG: Added pmos0, invKV, made invK allow longer than minimum lengths","","",""]
X

# Cell branchfactor{ic}
Cbranchfactor;1{ic}|artwork|1021415734000|1027724285000|E|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
NOpened-Thicker-Polygon|art@1||0.25|0|0.5|1|||ART_color()I78|trace()V[-0.25/-0.5,-0.25/0,0.25/0,-0.25/0,-0.25/0.5,0.25/0.5]
NThick-Circle|art@2||-0.5|-0.25|0.5|0.5|RRR||ART_color()I78|ART_degrees()F[0.0,3.1415927]
NOpened-Thicker-Polygon|art@3||-0.75|0|0.5|1|||ART_color()I78|trace()V[0.25/-0.5,-0.25/-0.5,-0.25/0.5,0.25/0.5]
NThick-Circle|art@4||-0.5|0.25|0.5|0.5|RRR||ART_color()I78|ART_degrees()F[0.0,3.1415927]
NOpened-Thicker-Polygon|art@5||0|0|3|4|||ART_color()I78|trace()V[-1.5/-2,-1.5/2,1.5/2,1.5/-2,-1.5/-2]
NPin|pin@0||2.5|0|0|0||W
NPin|pin@1||1.5|0|0|0||W
Nschematic:Bus_Pin|pin@2||2.5|0|0|0||
NPin|pin@3||-2.5|0|0|0||W
NPin|pin@4||-1.5|0|1|1||W
Nschematic:Bus_Pin|pin@5||-2.5|0|0|0||
AThicker|net@0||0|FS0|pin@0||2.5|0|pin@1||1.5|0|ART_color()I78
AThicker|net@1||0|FS0|pin@4||-1.5|0|pin@3||-2.5|0|ART_color()I78
Ein|D5G1;|pin@5||I
Eout|D5G1;|pin@2||O
X

# Cell branchfactor{sch}
Cbranchfactor;1{sch}|schematic|1021415734000|1028570639000||ATTR_BF(D5G1;HNPX-12;Y-8.25;)I1|ATTR_Delay(D5G1;HNPX-12;Y-5.5;)I0|ATTR_LEGATE(D5G1;HNPX-12;Y-11.5;)I1|ATTR_LEPARALLGRP(D5G1;HNPX-12;Y-6.5;)I-1|ATTR_M(D5G1;HNPX-12;Y-6.5;)I1|ATTR_S(D5G1;HNOJPX-12;Y-4.5;)SLE.getdrive()|ATTR_su(D5G1;HNPX-12;Y-9.5;)I1|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
Ibranchfactor;1{ic}|branchfa@0||18|8.5||E|D0G4;|ATTR_BF(D5G1.5;NPTY3;)I1|ATTR_Delay(D5G1;NPTX2;Y-2.25;)I0|ATTR_LEGATE(D5G1;NPTX5.75;Y3.75;)I1|ATTR_LEPARALLGRP(D5G1;NPTX4.75;Y1.5;)I-1|ATTR_M(D5G1;NPTX2;Y-1.25;)I1|ATTR_S(OJPT)S1|ATTR_su(D5G1;NPTX2;Y-5.25;)S""
NOff-Page|conn@0||-11|0|4|2||
NOff-Page|conn@1||8|0|4|2||
Ngeneric:Invisible-Pin|pin@0||-1.5|20|0|0|||ART_message(D5G6;)S[branchfactor]
Ngeneric:Invisible-Pin|pin@1||-2|14.5|0|0|||ART_message(D5G2;)S[Implements a branch factor of BF]
Awire|net@0||0|0|conn@1|a|6|0|conn@0|y|-9|0
Ein|D5G2;|conn@0|a|I|ATTR_le(D5G1;NOJY-2;)S@BF
Eout|D5G2;|conn@1|y|O
X

# Cell gallery{sch}
Cgallery;1{sch}|schematic|1044916063000|1117773519590||prototype_center()I[0,0]
ILEsettings;1{ic}|LEsettin@0||180|48.5||E|D5G4;|ATTR_LESETTINGS(D5G1;NPX-4.25;Y-4;)I1|ATTR_diffn(D6G1;NPX-4;Y-1.5;)F0.7|ATTR_diffp(D6G1;NPX-4;Y-2.5;)F0.7|ATTR_epsilon(D6G1;NPX-4;Y1.5;)F0.1|ATTR_gate_cap(D6G1;NPX-4;Y-0.5;)F0.4|ATTR_keeper_ratio(D6G1;NPX-4;Y-3.5;)F0.1|ATTR_max_iter(D6G1;NPX-4;Y0.5;)I40|ATTR_su(D6G1;NPX-4;Y3.5;)I4|ATTR_wire_ratio(D6G1;NPX-4;Y2.5;)F0.16
IorangeGeneric180:NMOS4f;1{ic}|NMOS4f@0||-7|33.5||E|D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)I2|ATTR_W(D6G1;NPX1.75;Y0.75;)I3|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IorangeGeneric180:NMOS4fwk;1{ic}|NMOS4fwk@0||17|33.5||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IredGeneric180:NMOS;1{ic}|NMOS@0||-19|42||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IorangeGeneric180:NMOSf;1{ic}|NMOSf@0||-19|33.5||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IorangeGeneric180:NMOSfwk;1{ic}|NMOSfwk@0||5|33.5||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IredGeneric180:NMOSwk;1{ic}|NMOSwk@0||5|42||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)S0
IorangeGeneric180:PMOS4f;1{ic}|PMOS4f@0||-7|0||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
IorangeGeneric180:PMOS4fwk;1{ic}|PMOS4fwk@0||17|0||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
IredGeneric180:PMOS;1{ic}|PMOS@0||-19|11||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
IorangeGeneric180:PMOSf;1{ic}|PMOSf@0||-19|0||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
IorangeGeneric180:PMOSfwk;1{ic}|PMOSfwk@0||5|0||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
IredGeneric180:PMOSwk;1{ic}|PMOSwk@0||5|11||E|D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0|0|0||AV
Ibranchfactor;1{ic}|branchfa@0||183|36.5||E|D5G4;|ATTR_BF(D5G1.5;NPY3;)I1|ATTR_Delay(D5G1;NPX2;Y-2.25;)I0|ATTR_LEGATE(D5G1;NPX5.75;Y3.75;)I1|ATTR_LEPARALLGRP(D5G1;NPX4.75;Y1.5;)I-1|ATTR_M(D5G1;NPX2;Y-1.25;)I1|ATTR_S(OJP)SLE.getdrive()|ATTR_su(D5G1;NPX2;Y-5.25;)I1
IredGeneric180:hifidely;1{ic}|hifidely@0||99|0||E|D0G4;
IredGeneric180:inv2i;1{ic}|inv2i@0||61|-22||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Iinv2i;1{ic}|inv2i@1||61|-12||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
IredGeneric180:inv2iHT;1{ic}|inv2iHT@0||93|-22||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Iinv2iHT;1{ic}|inv2iHT@1||93|-12||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
IredGeneric180:inv2iLT;1{ic}|inv2iLT@0||77|-22||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Iinv2iLT;2{ic}|inv2iLT@1||77|-12||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
IredGeneric180:inv2iV;1{ic}|inv2iV@0||153|11||E|D0G4;|ATTR_Delay(D5G1;NPX1.5;Y-4;)I100|ATTR_XN(D5G1.5;NPX1.5;Y-2.5;)I1|ATTR_XP(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Iinv2o;1{ic}|inv2o@0||177.5|10||E|D0G4;|ATTR_X(D5G1.5;NOJPX2;Y3;)S"LE.subdrive(\"invHT1\", \"X\")"|ATTR_delayH(D5G1;NPX2;Y-4.5;)I100|ATTR_delayL(D5G1;NPX2;Y-3.5;)I100|ATTR_su(P)I-1
IredGeneric180:inv;1{ic}|inv@0||-18.5|-22||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Iinv;1{ic}|inv@1||-18.5|-12||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
IinvCLK;1{ic}|invCLK@0||44.5|-12||E|D5G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
IredGeneric180:invCLK;1{ic}|invCLK@1||44.5|-22||E|D5G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IredGeneric180:invCTLn;1{ic}|invCTLn@0||106.5|-22||E|D0G4;|ATTR_Delay(D5G1;NPX1.5;Y1;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I2|ATTR_sloDelay(D5G1;NPX1.5;)I175
IinvCTLn;1{ic}|invCTLn@1||106.5|-12||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_sloDelay(D5G1;NPX1.75;Y-8.5;)I175|ATTR_su(P)I-1
IredGeneric180:invHT;1{ic}|invHT@0||13.5|-22||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IinvHT;1{ic}|invHT@1||13.5|-12||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
IredGeneric180:invK;1{ic}|invK@0||29.5|-22||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEKEEPER()I1|ATTR_LEPARALLGRP()I-1|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sweak0|ATTR_drive1(P)Sweak1|ATTR_su()I-1
IinvK;1{ic}|invK@1||29.5|-12||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEKEEPER(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sweak0|ATTR_drive1(P)Sweak1|ATTR_su(P)I-1
IredGeneric180:invKV;1{ic}|invKV@0||124.5|11||E|D0G4;|ATTR_Delay(D5G1;NPTX2;Y-4;)I100|ATTR_XN(D5G1.5;NPX1.5;Y-2.25;)I1|ATTR_XP(D5G1.5;NPX1.5;Y1.75;)I1|ATTR_drive0(PT)Sweak0|ATTR_drive1(PT)Sweak1
IredGeneric180:invLT;1{ic}|invLT@0||-2.5|-22||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IinvLT;1{ic}|invLT@1||-2.5|-12||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
IredGeneric180:invV;1{ic}|invV@0||140.5|11||E|D0G4;|ATTR_Delay(D5G1;NPX1.5;Y-4;)I100|ATTR_XN(D5G1.5;NPX1.75;Y-2.5;)I1|ATTR_XP(D5G1.5;NPX1.75;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IredGeneric180:invVn;1{ic}|invVn@0||95|11||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-3;)I100|ATTR_NPdrvR(D5G1;NPX2;Y-2;)I1|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IredGeneric180:invVp;1{ic}|invVp@0||109|11||E|D0G4;|ATTR_Delay(D5G1;NPX2;Y-3;)I100|ATTR_PNdrvR(D5G1;NPX2;Y-2;)I1|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IredGeneric180:mullerC;1{ic}|mullerC@0||141.5|-23||E|D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1