decoder24.vhd

来自「8位加法器VHDL源程序」· VHDL 代码 · 共 14 行

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.All;
ENTITY  DECODER24  IS
PORT (A,B : IN STD_LOGIC;
      y3,y2,y1,y0 : OUT STD_LOGIC);
END DECODER24;
ARCHITECTURE RTL OF DECODER24  IS
 begin
y3<=a and b;
y2<=a and (not b);
y1<=(not a) and b;
y0<=(not a) and (not b);
END  RTL;