adder8.vhd

来自「8位加法器VHDL源程序」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all; 
entity adder8 is
     port(a8: in std_logic_vector(7 downto 0);  
          b8: in std_logic_vector(7 downto 0);  
          c8:in std_logic;             
          co8: out std_logic;                   
          s8: out std_logic_vector(7 downto 0)); 
end adder8 ;
architecture hav of adder8 is
   component adder42                                             
     port(a4: in std_logic_vector(3 downto 0);  
          b4: in std_logic_vector(3 downto 0);  
          c4:in std_logic;             
          co4: out std_logic;                   
          s4: out std_logic_vector(3 downto 0));
    end component;
    signal carr : std_logic;
    begin  
    u1:  adder42 port map (a4=>a8(3 downto 0),b4=>b8(3 downto 0),c4=>c8,s4=>s8(3 downto 0),co4=>carr);
    u2:  adder42 port map (a4=>a8(7 downto 4),b4=>b8(7 downto 4),c4=>carr,s4=>s8(7 downto 4),co4=>co8);
 end hav;