adder.vhd

来自「8位加法器VHDL源程序」· VHDL 代码 · 共 19 行

library ieee;
use ieee.std_logic_1164.all;
entity adder is                          
      port(A:in std_logic;             
           B:in std_logic;
           Cin:in std_logic;             
           co:out std_logic;           
           S:out std_logic);      
end adder;
architecture hav of adder is          
      signal tmp1,tmp2 : std_logic;
      begin                             
        tmp1<=A xor B;
        tmp2<=tmp1 and Cin;
        S<=tmp1 xor Cin ;
        Co<=tmp2 or (A and B);
end hav;