adder8s.vhd

8位加法器VHDL源程序

library ieee;
use ieee.std_logic_1164.all; 
entity adder8s is
     port(x1,x2,cin,sc: in std_logic;
          l:in std_logic_vector(3 downto 0);
          co: out std_logic;                   
          s: out std_logic_vector(7 downto 0)); 
end adder8s ;
architecture hav of adder8s is
 component DECODER24
    PORT (A,B : IN STD_LOGIC;
          y3,y2,y1,y0 : OUT STD_LOGIC); 
 end component;
 component reg4
   PORT(D:IN STD_LOGIC_VECTOR(3 downto 0);
        EN,CLK:IN STD_LOGIC;
        Q:OUT STD_LOGIC_VECTOR(3 downto 0));
 end component;
 component adder8                                             
    port(a8: in std_logic_vector(7 downto 0);  
          b8: in std_logic_vector(7 downto 0);  
          c8:in std_logic;             
          co8: out std_logic;                   
          s8: out std_logic_vector(7 downto 0)); 
 end component;
    
signal i,j: std_logic_vector(7 downto 0);
signal k: std_logic_vector(0 to 3);
    begin  
    u1: DECODER24 port map (a=>x1,b=>x2,y3=>k(3),y2=>k(2),y1=>k(1),y0=>k(0));
    u2: reg4 port map (d=>l,en=>k(0),clk=>sc,q=>i(3 downto 0));
    u3: reg4 port map (d=>l,en=>k(1),clk=>sc,q=>i(7 downto 4));
    u4: reg4 port map (d=>l,en=>k(2),clk=>sc,q=>j(3 downto 0));
    u5: reg4 port map (d=>l,en=>k(3),clk=>sc,q=>j(7 downto 4));
    u6: adder8 port map (a8=>i,b8=>j,c8=>cin,co8=>co,s8=>s);
 end hav;