reg4.fit

8位加法器VHDL源程序

-- MAX+plus II Compiler Fit File      
-- Version 10.0 9/14/2000             
-- Compiled: 05/29/2005 17:13:39      

-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "reg4"
BEGIN

    DEVICE = "EP1K10TC100-1";

    "CLK"                          : INPUT_PIN  = 39     ;
    "D0"                           : INPUT_PIN  = 40     ;
    "D1"                           : INPUT_PIN  = 89     ;
    "D2"                           : INPUT_PIN  = 91     ;
    "D3"                           : INPUT_PIN  = 90     ;
    "EN"                           : INPUT_PIN  = 38     ;
    "Q0"                           : OUTPUT_PIN = 69     ;
    "Q1"                           : OUTPUT_PIN = 68     ;
    "Q2"                           : OUTPUT_PIN = 71     ;
    "Q3"                           : OUTPUT_PIN = 70     ;
    ":7"                           : LOCATION   = LC2_A4 ;
    ":9"                           : LOCATION   = LC1_A4 ;
    ":11"                          : LOCATION   = LC6_A4 ;
    ":13"                          : LOCATION   = LC5_A4 ;

END;

INTERNAL_INFO "reg4"
BEGIN
	DEVICE = EP1K10TC100-1;
    OD5P39  : LORAX = "1:FB5->LC2_A4,->LC1_A4,->LC6_A4,->LC5_A4|";
    OD3P40  : LORAX = "1:FB3|2:FH3R0,PA5R0C3->LC5_A4||";
    OD1P89  : LORAX = "1:FB1|2:FH1R0,PA20R0C3->LC6_A4||";
    OD0P91  : LORAX = "1:FB0|2:FH0R0,PA0R0C3->LC1_A4||";
    OD4P90  : LORAX = "1:FB4|2:CH0R0,PA19R0C3->LC2_A4||";
    OD2P38  : LORAX = "1:FB2|2:FH2R0,PA6R0C3->LC2_A4,->LC1_A4,->LC6_A4,->LC5_A4||";
    LC2_A4  : LORAX = "1:MSW2R0C2,G14R0->OH10R0P70|";
    LC1_A4  : LORAX = "1:MSW0R0C3,HHL19R0->OH8R0P71|";
    LC6_A4  : LORAX = "1:MSW6R0C2,G87R0->OH14R0P68|";
    LC5_A4  : LORAX = "1:MSW4R0C3,HHL38R0->OH12R0P69|";
	LC2_A4  : LORAX2 = "X, OD4P90, OD2P38, LC2_A4";
	LC1_A4  : LORAX2 = "X, OD0P91, OD2P38, LC1_A4";
	LC6_A4  : LORAX2 = "X, OD1P89, OD2P38, LC6_A4";
	LC5_A4  : LORAX2 = "X, OD3P40, OD2P38, LC5_A4";
END;