adder42.vhd

来自「8位加法器VHDL源程序」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all; 
entity adder42 is
 --generic (n:integer:=3);                            
      port(a4: in std_logic_vector(3 downto 0);  
          b4: in std_logic_vector(3 downto 0);  
          c4:in std_logic;             
          co4: out std_logic;                   
          s4: out std_logic_vector(3 downto 0)); 
end adder42 ;
architecture hav of adder42 is
   component adder                                             
     port(a: in std_logic;
          b: in std_logic;
          cin: in std_logic;
          co:out std_logic;
          s:out std_logic);
    end component;
  signal carr:std_logic_vector(2 downto 0);
   begin
    label1:                                        
            for i in 0 to 3 generate
    label2: if (i=0) generate  
            adderx: adder port map (a4(i),b4(i),c4,carr(i),s4(i));
            end generate label2;
    label3: if(i=3) generate 
            adderx: adder port map(a4(i),b4(i),carr(i-1),co4,s4(i));
            end generate label3;
    label4: if ((i/=0) and (i/=3)) generate
            adderx: adder port map(a4(i),b4(i),carr(i-1),carr(i),s4(i));
            end generate  label4;
            end generate label1;
    end hav;