adder8s.hif

8位加法器VHDL源程序

HIF003
--
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	adder.vhd
	{
		adder [] [U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			5 [] [];
		}
	}
	adder42.vhd
	{
		adder42 [] [U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			4 [] [];
		}
	}
	adder8.vhd
	{
		adder8 [] [U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			3 [] [];
		}
	}
	reg4.vhd
	{
		reg4 [] [U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			2 [] [];
		}
	}
	decoder24.vhd
	{
		decoder24 [] [U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			1 [] [];
		}
	}
	adder8s.vhd
	{
		adder8s [] [U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			0 [] [];
		}
	}
}
TREE
{
	adder8s::(0,0):(0): adder8s.vhd
	{
		decoder24:1:(30,9):(258,u1): decoder24.vhd;
		reg4:2:(31,9):(259,u2): reg4.vhd;
		reg4:2:(32,9):(260,u3): reg4.vhd;
		reg4:2:(33,9):(261,u4): reg4.vhd;
		reg4:2:(34,9):(262,u5): reg4.vhd;
		adder8:3:(35,9):(263,u6): adder8.vhd
		{
			adder42:4:(20,10):(132,u1): adder42.vhd
			{
				adder:5:(24,21):(147,adderx): adder.vhd;
				adder:5:(30,21):(148,adderx~61): adder.vhd;
				adder:5:(30,21):(149,adderx~91): adder.vhd;
				adder:5:(27,21):(150,adderx~114): adder.vhd;
			}
			adder42:4:(21,10):(133,u2): adder42.vhd
			{
				adder:5:(24,21):(147,adderx): adder.vhd;
				adder:5:(30,21):(148,adderx~61): adder.vhd;
				adder:5:(30,21):(149,adderx~91): adder.vhd;
				adder:5:(27,21):(150,adderx~114): adder.vhd;
			}
		}
	}
}