fp1.vhd

来自「很精典的一个分频程序」· VHDL 代码 · 共 30 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fp1 IS
PORT(clk:IN STD_LOGIC;
 outp: out STD_LOGIC
);
END fp1;
ARCHITECTURE rtl OF fp1 IS
signal count:integer;
begin

process(clk)
begin 
	if(clk'event and clk='1') then
	if(count=2499)then
			count<=0;
	else 
	
			count<=count+1;
		if (count<1250) then
			outp<='0';
		else
			outp<='1';
		end if;
	end if;
	end if;
end process;
end rtl;