timer.vhd

来自「很精典的一个分频程序」· VHDL 代码 · 共 111 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY timer IS
PORT(clk2,clk,c1,c2,c3,en:IN STD_LOGIC;
 outp: out STD_LOGIC
);
END timer;
ARCHITECTURE rtl OF timer IS
signal count,count1,count2,count3,count4,count5:integer;
signal cnt:std_logic;
signal cen1:std_logic_vector(2 downto 0);
begin
outp<=cnt;
cen1<=c1&c2&c3;

process(clk)
begin 
if clk2'event and clk2='1' then
case cen1 is
when"001"=>
    
	  if(clk'event and clk='1') then
	  if en='1' then
	     count<=count+1;
	  else
	     count<=0;
	  end if;
	 
	    if(count>30)then
			cnt<='0';
	    else 
		    cnt<='1';
	   end if;
	   end if;
when"010"=>
     if(clk'event and clk='1') then
	  if en='1' then
	     count1<=count1+1;
	  else
	     count1<=0;
	  end if;
	 
	    if(count1>60)then
			cnt<='0';
	    else 
		    cnt<='1';
	   end if;
	   end if;
when"011"=>
     if(clk'event and clk='1') then
	  if en='1' then
	     count2<=count2+1;
	  else
	     count2<=0;
	  end if;
	 
	    if(count2>120)then
			cnt<='0';
	    else 
		    cnt<='1';
	   end if;
	   end if;
when"100"=>
     if(clk'event and clk='1') then
	  if en='1' then
	     count3<=count3+1;
	  else
	     count3<=0;
	  end if;
	 
	    if(count3>180)then
			cnt<='0';
	    else 
		    cnt<='1';
	   end if;
	   end if;
when"101"=>
     if(clk'event and clk='1') then
	  if en='1' then
	     count4<=count4+1;
	  else
	     count4<=0;
	  end if;
	 
	    if(count4>240)then
			cnt<='0';
	    else 
		    cnt<='1';
	   end if;
	   end if;
when"110"=>
     if(clk'event and clk='1') then
	  if en='1' then
	     count5<=count5+1;
	  else
	     count5<=0;
	  end if;
	 
	    if(count5>300)then
			cnt<='0';
	    else 
		    cnt<='1';
	   end if;
	   end if;
when others=>null;
end case;	
end if;
end process;
end rtl;