zhengxuan.vhd

很精典的一个分频程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY zhengxuan IS
PORT(clk:IN STD_LOGIC;
 
 outp: out STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END zhengxuan;
ARCHITECTURE rtl OF zhengxuan IS

signal l:integer range 63 downto 0;
signal data:integer;
begin
outp<=conv_std_logic_vector(data,10);
process(clk)

begin

if clk'event and clk='1' then
  l<=l+1;
 
case l is
 when 00=>data<=512;
	when 01=>data<=562;
	when 02=>data<=611;
	when 03=>data<=660;
	when 04=>data<=707;
	when 05=>data<=753;
	when 06=>data<=796;
	when 07=>data<=836;
	when 08=>data<=874;
	when 09=>data<=907;
	when 10=>data<=937;
	when 11=>data<=963;
	when 12=>data<=985;
	when 13=>data<=1001;
	when 14=>data<=1014;
	when 15=>data<=1021;
	when 16=>data<=1023;
	when 17=>data<=1021;
	when 18=>data<=1014;
	when 19=>data<=1001;
	when 20=>data<=985;
	when 21=>data<=963;
	when 22=>data<=937;
	when 23=>data<=907;
	when 24=>data<=874;
	when 25=>data<=836;
	when 26=>data<=796;
	when 27=>data<=753;
	when 28=>data<=707;
	when 29=>data<=660;
	when 30=>data<=611;
	when 31=>data<=562;
	when 32=>data<=511;
	when 33=>data<=461;
	when 34=>data<=412;
	when 35=>data<=363;
	when 36=>data<=316;
	when 37=>data<=257;
	when 38=>data<=227;
	when 39=>data<=187;
	when 40=>data<=149;
	when 41=>data<=116;
	when 42=>data<=86;
	when 43=>data<=60;
	when 44=>data<=38;
	when 45=>data<=22;
	when 46=>data<=9;
	when 47=>data<=2;
	when 48=>data<=0;
	when 49=>data<=2;
	when 50=>data<=9;
	when 51=>data<=22;
	when 52=>data<=38;
	when 53=>data<=60;
	when 54=>data<=86;
	when 55=>data<=116;
	when 56=>data<=149;
	when 57=>data<=187;
	when 58=>data<=227;
	when 59=>data<=257;
	when 60=>data<=316;
	when 61=>data<=363;
	when 62=>data<=412;
	when 63=>data<=461;
--when 00=>q<="1111111111";when 01=>q<="1111111000";when 02=>q<="1111110000";when 03=>q<="1111100100";
--when 04=>q<="1111010100";when 05=>q<="1110111100";when 06=>q<="1110100100";when 07=>q<="1110000100";
--when 08=>q<="1101100100";when 09=>q<="1100111100";when 10=>q<="1100010100";when 11=>q<="1011101000";
--when 12=>q<="1000100100";when 13=>q<="1010111000";when 14=>q<="1001011000";when 15=>q<="1010001000";
--when 16=>q<="0111110000";when 17=>q<="0111000000";when 18=>q<="0110001100";when 19=>q<="0101011100";
--when 20=>q<="0100101100";when 21=>q<="0100000000";when 22=>q<="0011010100";when 23=>q<="0010101100";
--when 24=>q<="0010001000";when 25=>q<="0001101000";when 26=>q<="0001001100";when 27=>q<="0000110100";
--when 28=>q<="0000100000";when 29=>q<="0000010000";when 30=>q<="0000000100";when 31=>q<="0000000000";
--when 32=>q<="0000000000";when 33=>q<="0000000100";when 34=>q<="0000010000";when 35=>q<="0000100000";
--when 36=>q<="0000110100";when 37=>q<="0001001100";when 38=>q<="0001101000";when 39=>q<="0010001000";
--when 40=>q<="0010101100";when 41=>q<="0011010100";when 42=>q<="0100000000";when 43=>q<="0100101100";
--when 44=>q<="0101011100";when 45=>q<="0110001100";when 46=>q<="0111000000";when 47=>q<="0111110000";
--when 48=>q<="1010001000";when 49=>q<="1001011000";when 50=>q<="1010111000";when 51=>q<="1000100100";
--when 52=>q<="1011101000";when 53=>q<="1100010100";when 54=>q<="1100111100";when 55=>q<="1101100100";
--when 56=>q<="1110000100";when 57=>q<="1110100100";when 58=>q<="1110111100";when 59=>q<="1111010100";
--when 60=>q<="1111100100";when 61=>q<="1111110000";when 62=>q<="1111111000";when 63=>q<="1111111111";
when others=>null;
end case; 
end if;
end process;
end rtl;