fsq.map.rpt

很精典的一个分频程序

; fptd:u2|a[7]                                  ;    ;
; fptd:u2|a[8]                                  ;    ;
; fptd:u2|a[9]                                  ;    ;
; fptd:u2|a[10]                                 ;    ;
; Number of user-specified and inferred latches ; 10 ;
+-----------------------------------------------+----+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 102   ;
; Number of registers using Synchronous Clear  ; 39    ;
; Number of registers using Synchronous Load   ; 7     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 19    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |fsq|xb:u7|outp[6]         ;
; 3:1                ; 11 bits   ; 22 LEs        ; 0 LEs                ; 22 LEs                 ; Yes        ; |fsq|fptd:u2|\label2:c[0]  ;
; 4:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |fsq|sanjiaobo:u5|q[4]     ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |fsq|sanjiaobo:u5|q[7]     ;
; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; No         ; |fsq|xb:u7|outp4[4]        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/altera/quartus50/fsq/fsq.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sun Jul 15 14:23:02 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fsq -c fsq
Info: Found 2 design units, including 1 entities, in source file fangbo.vhd
    Info: Found design unit 1: fangbo-rtl
    Info: Found entity 1: fangbo
Info: Found 2 design units, including 1 entities, in source file sanjiaobo.vhd
    Info: Found design unit 1: sanjiaobo-rtl
    Info: Found entity 1: sanjiaobo
Info: Found 2 design units, including 1 entities, in source file zhengxuan.vhd
    Info: Found design unit 1: zhengxuan-rtl
    Info: Found entity 1: zhengxuan
Warning: Can't analyze file -- file D:/altera/quartus50/fsq/fp.vhd is missing
Warning: Can't analyze file -- file D:/altera/quartus50/fsq/td.vhd is missing
Info: Found 2 design units, including 1 entities, in source file fsq.vhd
    Info: Found design unit 1: fsq-rtl
    Info: Found entity 1: fsq
Info: Found 2 design units, including 1 entities, in source file xb.vhd
    Info: Found design unit 1: xb-rtl
    Info: Found entity 1: xb
Info: Found 2 design units, including 1 entities, in source file da_tran.vhd
    Info: Found design unit 1: da_tran-rtl
    Info: Found entity 1: da_tran
Info: Found 2 design units, including 1 entities, in source file piso.vhd
    Info: Found design unit 1: piso-trl
    Info: Found entity 1: piso
Info: Found 2 design units, including 1 entities, in source file fptd.vhd
    Info: Found design unit 1: fptd-subdivision
    Info: Found entity 1: fptd
Info: Found 2 design units, including 1 entities, in source file ExpWave.vhd
    Info: Found design unit 1: ExpWave-Exp_arc
    Info: Found entity 1: ExpWave
Info: Elaborating entity "fsq" for the top level hierarchy
Info: (10035) Verilog HDL or VHDL information at fsq.vhd(16): object "asd" declared but not used
Info: Elaborating entity "fptd" for hierarchy "fptd:u2"
Info: Elaborating entity "zhengxuan" for hierarchy "zhengxuan:u3"
Info: VHDL Case Statement information at zhengxuan.vhd(105): OTHERS choice is never selected
Info: Elaborating entity "fangbo" for hierarchy "fangbo:u4"
Info: Elaborating entity "sanjiaobo" for hierarchy "sanjiaobo:u5"
Info: Elaborating entity "ExpWave" for hierarchy "ExpWave:u6"
Info: VHDL Case Statement information at ExpWave.vhd(47): OTHERS choice is never selected
Info: Elaborating entity "xb" for hierarchy "xb:u7"
Info: (10035) Verilog HDL or VHDL information at xb.vhd(13): object "qwe1" declared but not used
Info: (10035) Verilog HDL or VHDL information at xb.vhd(13): object "qwe" declared but not used
Warning: VHDL Process Statement warning at xb.vhd(24): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(36): signal "q" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(38): signal "q1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(40): signal "q2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(42): signal "q3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: VHDL Case Statement information at xb.vhd(43): OTHERS choice is never selected
Warning: VHDL Process Statement warning at xb.vhd(45): signal "outp4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(50): signal "outp3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(51): signal "outp3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(52): signal "outp3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(53): signal "outp3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: VHDL Case Statement information at xb.vhd(54): OTHERS choice is never selected
Warning: VHDL Process Statement warning at xb.vhd(56): signal "outp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "da_tran" for hierarchy "da_tran:u8"
Info: (10035) Verilog HDL or VHDL information at da_tran.vhd(17): object "clkout" declared but not used
Warning: VHDL Process Statement warning at da_tran.vhd(35): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "piso" for hierarchy "piso:u9"
Warning: Reduced register "piso:u9|tmp[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "piso:u9|tmp[1]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "fangbo:u4|outp[8]" merged to single register "fangbo:u4|outp[9]"
    Info: Duplicate register "fangbo:u4|outp[7]" merged to single register "fangbo:u4|outp[9]"
    Info: Duplicate register "fangbo:u4|outp[6]" merged to single register "fangbo:u4|outp[9]"
    Info: Duplicate register "fangbo:u4|outp[5]" merged to single register "fangbo:u4|outp[9]"
    Info: Duplicate register "fangbo:u4|outp[4]" merged to single register "fangbo:u4|outp[9]"
    Info: Duplicate register "fangbo:u4|outp[3]" merged to single register "fangbo:u4|outp[9]"
    Info: Duplicate register "fangbo:u4|outp[2]" merged to single register "fangbo:u4|outp[9]"
    Info: Duplicate register "fangbo:u4|outp[1]" merged to single register "fangbo:u4|outp[9]"
Warning: Reduced register "xb:u7|outp[9]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "fangbo:u4|l[0]" merged to single register "sanjiaobo:u5|l[0]"
    Info: Duplicate register "zhengxuan:u3|l[0]" merged to single register "sanjiaobo:u5|l[0]"
    Info: Duplicate register "zhengxuan:u3|l[1]" merged to single register "sanjiaobo:u5|l[1]"
    Info: Duplicate register "fangbo:u4|l[1]" merged to single register "sanjiaobo:u5|l[1]"
    Info: Duplicate register "zhengxuan:u3|l[2]" merged to single register "fangbo:u4|l[2]"
    Info: Duplicate register "fangbo:u4|l[2]" merged to single register "sanjiaobo:u5|l[2]"
    Info: Duplicate register "zhengxuan:u3|l[3]" merged to single register "fangbo:u4|l[3]"
    Info: Duplicate register "fangbo:u4|l[3]" merged to single register "sanjiaobo:u5|l[3]"
    Info: Duplicate register "zhengxuan:u3|l[4]" merged to single register "fangbo:u4|l[4]"
    Info: Duplicate register "fangbo:u4|l[4]" merged to single register "sanjiaobo:u5|l[4]"
    Info: Duplicate register "zhengxuan:u3|l[5]" merged to single register "fangbo:u4|l[5]"
    Info: Duplicate register "fangbo:u4|outp[9]" merged to single register "zhengxuan:u3|data[9]", power-up level changed
    Info: Duplicate register "fangbo:u4|l[5]" merged to single register "sanjiaobo:u5|l[5]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "sanjiaobo:u5|l[0]" merged to single register "ExpWave:u6|tmp[0]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "ExpWave:u6|tmp[5]" merged to single register "ExpWave:u6|d[9]", power-up level changed
Info: Duplicate registers merged to single register
    Info: Duplicate register "ExpWave:u6|tmp[1]" merged to single register "sanjiaobo:u5|l[1]"
    Info: Duplicate register "ExpWave:u6|tmp[2]" merged to single register "sanjiaobo:u5|l[2]"
    Info: Duplicate register "ExpWave:u6|tmp[3]" merged to single register "sanjiaobo:u5|l[3]"
    Info: Duplicate register "ExpWave:u6|tmp[4]" merged to single register "sanjiaobo:u5|l[4]"
Warning: Latch fptd:u2|a[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[0]
Warning: Latch fptd:u2|a[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[0]
Warning: Latch fptd:u2|a[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[2]
Warning: Latch fptd:u2|a[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[1]
Warning: Latch fptd:u2|a[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[0]
Warning: Latch fptd:u2|a[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[0]
Warning: Latch fptd:u2|a[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[1]
Warning: Latch fptd:u2|a[8] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[0]
Warning: Latch fptd:u2|a[9] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[0]
Warning: Latch fptd:u2|a[10] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[1]
Info: Implemented 269 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 4 output pins
    Info: Implemented 255 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 37 warnings
    Info: Processing ended: Sun Jul 15 14:23:23 2007
    Info: Elapsed time: 00:00:22