📄 fsq.fit.rpt
字号:
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 2 ;
; 7 ; 3 ;
; 8 ; 5 ;
; 9 ; 6 ;
; 10 ; 11 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.05) ; Number of LABs (Total = 37) ;
+------------------------------------+------------------------------+
; 1 Clock ; 27 ;
; 1 Clock enable ; 5 ;
; 1 Sync. clear ; 5 ;
; 1 Sync. load ; 1 ;
; 2 Clocks ; 1 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 6.95) ; Number of LABs (Total = 37) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 7 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 3 ;
; 8 ; 4 ;
; 9 ; 7 ;
; 10 ; 9 ;
; 11 ; 1 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 4.14) ; Number of LABs (Total = 37) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 9 ;
; 2 ; 3 ;
; 3 ; 6 ;
; 4 ; 4 ;
; 5 ; 6 ;
; 6 ; 2 ;
; 7 ; 2 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 4 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 8.86) ; Number of LABs (Total = 37) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 4 ;
; 3 ; 3 ;
; 4 ; 5 ;
; 5 ; 3 ;
; 6 ; 0 ;
; 7 ; 2 ;
; 8 ; 2 ;
; 9 ; 2 ;
; 10 ; 4 ;
; 11 ; 1 ;
; 12 ; 1 ;
; 13 ; 1 ;
; 14 ; 1 ;
; 15 ; 0 ;
; 16 ; 0 ;
; 17 ; 0 ;
; 18 ; 2 ;
; 19 ; 1 ;
; 20 ; 2 ;
; 21 ; 2 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Sun Jul 15 14:23:28 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off fsq -c fsq
Info: Selected device EPM1270T144C5 for design "fsq"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM570T144C5 is compatible
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144I5 is compatible
Info: Device EPM1270T144C5ES is compatible
Info: No exact pin location assignment(s) for 1 pins of 14 total pins
Info: Pin clk4 not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted some destinations of signal "da_tran:u8|dsclk" to use Global clock
Info: Destination "dsclk" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "fptd:u2|q" to use Global clock
Info: Destination "clk4" may be non-global or may not use global clock
Info: Destination "da_tran:u8|counter1[31]" may be non-global or may not use global clock
Info: Destination "fptd:u2|q" may be non-global or may not use global clock
Info: Destination "da_tran:u8|counter1[2]" may be non-global or may not use global clock
Info: Destination "da_tran:u8|counter1[3]" may be non-global or may not use global clock
Info: Destination "da_tran:u8|counter1[4]" may be non-global or may not use global clock
Info: Destination "da_tran:u8|process2~294" may be non-global or may not use global clock
Info: Destination "da_tran:u8|counter1[5]" may be non-global or may not use global clock
Info: Destination "da_tran:u8|counter1[6]" may be non-global or may not use global clock
Info: Destination "da_tran:u8|counter1[7]" may be non-global or may not use global clock
Info: Limited to 10 non-global destinations
Info: Automatically promoted signal "fptd:u2|Mux~349" to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)
Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 10 total pin(s) used -- 16 pins available
Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 3 total pin(s) used -- 27 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 30 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 30 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to pin delay of 8.305 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y9; Fanout = 4; REG Node = 'da_tran:u8|counter1[2]'
Info: 2: + IC(0.620 ns) + CELL(0.740 ns) = 1.360 ns; Loc. = LAB_X13_Y9; Fanout = 1; COMB Node = 'da_tran:u8|process2~294'
Info: 3: + IC(1.499 ns) + CELL(0.914 ns) = 3.773 ns; Loc. = LAB_X14_Y10; Fanout = 1; COMB Node = 'da_tran:u8|process2~298'
Info: 4: + IC(0.896 ns) + CELL(0.740 ns) = 5.409 ns; Loc. = LAB_X15_Y10; Fanout = 12; COMB Node = 'da_tran:u8|process2~304'
Info: 5: + IC(0.574 ns) + CELL(2.322 ns) = 8.305 ns; Loc. = PIN_111; Fanout = 0; PIN Node = 'cs'
Info: Total cell delay = 4.716 ns ( 56.79 % )
Info: Total interconnect delay = 3.589 ns ( 43.21 % )
Info: Fitter placement operations ending: elapsed time is 00:00:08
Info: Fitter routing operations beginning
Info: Average interconnect usage is 5% of the available device resources. Peak interconnect usage is 5%.
Info: Fitter routing operations ending: elapsed time is 00:00:02
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sun Jul 15 14:23:57 2007
Info: Elapsed time: 00:00:30
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