fsq.vhd

很精典的一个分频程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fsq IS  --发生器
PORT(
 clk:in std_logic;
 en ,c1,c2,c3:in std_logic;
  m,k,w1,w2: in std_logic;
mp1:in std_logic_vector(3 downto 0);
      mk:in std_logic_vector(1 downto 0);
  td1:in std_logic_vector(3 downto 0);
 cs,dsclk,din,clk4: out STD_LOGIC
 
);
END fsq;
ARCHITECTURE rtl OF fsq IS
signal asd :std_logic_vector(11 downto 0);
signal la,la1,la2,outp6,cs2,clk3,clk7:std_logic;
signal q3:std_logic_vector(9 downto 0);
signal q4:std_logic_vector(9 downto 0);
signal q5,q6:std_logic_vector(9 downto 0);
signal outbx,outbx1:STD_LOGIC_VECTOR(9 DOWNTO 0);
component fp1 
PORT(clk:IN STD_LOGIC;
 outp: out STD_LOGIC
);
END component;
component fp2 
PORT(clk:IN STD_LOGIC;
 outp: out STD_LOGIC
);
END component;
component timer 
PORT(clk2,clk,c1,c2,c3,en:IN STD_LOGIC;
 outp: out STD_LOGIC
);
END component;
component fptd 
PORT(
        td1:in std_logic_vector(3 downto 0);
        clk: in std_logic;
        q:out std_logic);
end component;


component zhengxuan 
PORT(clk:IN STD_LOGIC;
 outp: out STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END component;
component sanjiaobo
PORT(clk:IN STD_LOGIC; 
 outp: out STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END component;
component fangbo
PORT(clk:IN STD_LOGIC; 
 outp: out STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END component;
component ExpWave                                                    
  port(clk : in std_logic;
       outp: out std_logic_vector(9 downto 0));
END component;
component xb 
PORT(--clk:IN STD_LOGIC;
     clk,m,k,en,w1,w2: in std_logic;
     q,q1,q2,q3:in STD_LOGIC_VECTOR(9 DOWNTO 0);
 outp: out STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END component;
component mp 
PORT(clk:in std_logic;
      
      mp1:in std_logic_vector(3 downto 0);
      mk:in std_logic_vector(1 downto 0);
      data_in:in std_logic_vector(9 downto 0);
	data_out:out std_logic_vector(9 downto 0));
END component;
component da_tran
PORT(clk1:in STD_LOGIC;
     cnt4:in std_logic;
     rst:in std_logic;
     qin:in std_logic_vector(9 downto 0);
 cs,dsclk: out STD_LOGIC
);
END component;
 component piso 
PORT(data :IN std_logic_vector(9 DOWNTO 0);
             sclk,sl : IN  std_logic;
			 q: OUT STD_LOGIC);
END component;
begin
cs<=cs2;
dsclk<=clk3;
clk4<=la;
u1:fp1
port map(clk,la1);
u2:fp2
port map(la1,la2);
u3:timer
port map(clk,la2,c1,c2,c3,en,outp6);
u4:fptd
port map(td1,clk,la);
u5:zhengxuan
port map(la,q3);
u6:fangbo
port map(la,q4);
u7:sanjiaobo
port map(la,q5);
u8:ExpWave
port map(la,q6);
u9:xb
port map(clk,m,k,en,w1,w2,q3,q4,q5,q6,outbx);
u10:mp
port map(la,mp1,mk,outbx,outbx1);
u11:da_tran
--port map(clk,outp6,la,outbx1,cs2,clk3);
port map(clk,outp6,la,outbx1,cs2,clk3);
u12:piso
port map(outbx1,clk3,cs2,din);

end rtl;