fsq.map.rpt

很精典的一个分频程序

    Info: Found design unit 1: fptd-subdivision
    Info: Found entity 1: fptd
Info: Found 2 design units, including 1 entities, in source file ExpWave.vhd
    Info: Found design unit 1: ExpWave-Exp_arc
    Info: Found entity 1: ExpWave
Info: Found 2 design units, including 1 entities, in source file fp1.vhd
    Info: Found design unit 1: fp1-rtl
    Info: Found entity 1: fp1
Info: Found 2 design units, including 1 entities, in source file fp2.vhd
    Info: Found design unit 1: fp2-rtl
    Info: Found entity 1: fp2
Info: Found 2 design units, including 1 entities, in source file timer.vhd
    Info: Found design unit 1: timer-rtl
    Info: Found entity 1: timer
Info: Found 2 design units, including 1 entities, in source file mp.vhd
    Info: Found design unit 1: mp-rtl
    Info: Found entity 1: mp
Info: Elaborating entity "fsq" for the top level hierarchy
Info: (10035) Verilog HDL or VHDL information at fsq.vhd(18): object "asd" declared but not used
Info: (10035) Verilog HDL or VHDL information at fsq.vhd(19): object "clk7" declared but not used
Info: Elaborating entity "fp1" for hierarchy "fp1:u1"
Info: Elaborating entity "fp2" for hierarchy "fp2:u2"
Info: Elaborating entity "timer" for hierarchy "timer:u3"
Warning: VHDL Process Statement warning at timer.vhd(20): signal "clk2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "fptd" for hierarchy "fptd:u4"
Info: Elaborating entity "zhengxuan" for hierarchy "zhengxuan:u5"
Info: VHDL Case Statement information at zhengxuan.vhd(105): OTHERS choice is never selected
Info: Elaborating entity "fangbo" for hierarchy "fangbo:u6"
Info: Elaborating entity "sanjiaobo" for hierarchy "sanjiaobo:u7"
Info: Elaborating entity "ExpWave" for hierarchy "ExpWave:u8"
Info: VHDL Case Statement information at ExpWave.vhd(47): OTHERS choice is never selected
Info: Elaborating entity "xb" for hierarchy "xb:u9"
Info: (10035) Verilog HDL or VHDL information at xb.vhd(13): object "qwe1" declared but not used
Info: (10035) Verilog HDL or VHDL information at xb.vhd(13): object "qwe" declared but not used
Warning: VHDL Process Statement warning at xb.vhd(24): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(36): signal "q" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(38): signal "q1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(40): signal "q2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(42): signal "q3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: VHDL Case Statement information at xb.vhd(43): OTHERS choice is never selected
Warning: VHDL Process Statement warning at xb.vhd(45): signal "outp4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(50): signal "outp3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(51): signal "outp3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(52): signal "outp3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at xb.vhd(53): signal "outp3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: VHDL Case Statement information at xb.vhd(54): OTHERS choice is never selected
Warning: VHDL Process Statement warning at xb.vhd(56): signal "outp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "mp" for hierarchy "mp:u10"
Info: VHDL Case Statement information at mp.vhd(55): OTHERS choice is never selected
Info: Elaborating entity "da_tran" for hierarchy "da_tran:u11"
Info: (10035) Verilog HDL or VHDL information at da_tran.vhd(18): object "clkout" declared but not used
Warning: VHDL Process Statement warning at da_tran.vhd(36): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "piso" for hierarchy "piso:u12"
Warning: Reduced register "piso:u12|tmp[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "piso:u12|tmp[1]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "mp:u10|waveout[8]" merged to single register "mp:u10|waveout[9]"
    Info: Duplicate register "mp:u10|waveout[7]" merged to single register "mp:u10|waveout[9]"
    Info: Duplicate register "mp:u10|waveout[6]" merged to single register "mp:u10|waveout[9]"
    Info: Duplicate register "mp:u10|waveout[5]" merged to single register "mp:u10|waveout[9]"
    Info: Duplicate register "mp:u10|waveout[4]" merged to single register "mp:u10|waveout[9]"
    Info: Duplicate register "mp:u10|waveout[3]" merged to single register "mp:u10|waveout[9]"
    Info: Duplicate register "mp:u10|waveout[2]" merged to single register "mp:u10|waveout[9]"
    Info: Duplicate register "mp:u10|waveout[1]" merged to single register "mp:u10|waveout[9]"
    Info: Duplicate register "mp:u10|waveout[0]" merged to single register "mp:u10|waveout[9]"
    Info: Duplicate register "fangbo:u6|outp[8]" merged to single register "fangbo:u6|outp[9]"
    Info: Duplicate register "fangbo:u6|outp[7]" merged to single register "fangbo:u6|outp[9]"
    Info: Duplicate register "fangbo:u6|outp[6]" merged to single register "fangbo:u6|outp[9]"
    Info: Duplicate register "fangbo:u6|outp[5]" merged to single register "fangbo:u6|outp[9]"
    Info: Duplicate register "fangbo:u6|outp[4]" merged to single register "fangbo:u6|outp[9]"
    Info: Duplicate register "fangbo:u6|outp[3]" merged to single register "fangbo:u6|outp[9]"
    Info: Duplicate register "fangbo:u6|outp[2]" merged to single register "fangbo:u6|outp[9]"
    Info: Duplicate register "fangbo:u6|outp[1]" merged to single register "fangbo:u6|outp[9]"
Warning: Reduced register "xb:u9|outp[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "mp:u10|data_out[9]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "zhengxuan:u5|l[0]" merged to single register "sanjiaobo:u7|l[0]"
    Info: Duplicate register "fangbo:u6|l[0]" merged to single register "sanjiaobo:u7|l[0]"
    Info: Duplicate register "fangbo:u6|l[1]" merged to single register "sanjiaobo:u7|l[1]"
    Info: Duplicate register "zhengxuan:u5|l[1]" merged to single register "sanjiaobo:u7|l[1]"
    Info: Duplicate register "zhengxuan:u5|l[2]" merged to single register "fangbo:u6|l[2]"
    Info: Duplicate register "fangbo:u6|l[2]" merged to single register "sanjiaobo:u7|l[2]"
    Info: Duplicate register "zhengxuan:u5|l[3]" merged to single register "fangbo:u6|l[3]"
    Info: Duplicate register "fangbo:u6|l[3]" merged to single register "sanjiaobo:u7|l[3]"
    Info: Duplicate register "zhengxuan:u5|l[4]" merged to single register "fangbo:u6|l[4]"
    Info: Duplicate register "fangbo:u6|l[4]" merged to single register "sanjiaobo:u7|l[4]"
    Info: Duplicate register "zhengxuan:u5|l[5]" merged to single register "fangbo:u6|l[5]"
    Info: Duplicate register "fangbo:u6|outp[9]" merged to single register "zhengxuan:u5|data[9]", power-up level changed
    Info: Duplicate register "fangbo:u6|l[5]" merged to single register "sanjiaobo:u7|l[5]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "sanjiaobo:u7|l[0]" merged to single register "mp:u10|counter1[0]"
    Info: Duplicate register "ExpWave:u8|tmp[0]" merged to single register "mp:u10|counter1[0]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "ExpWave:u8|tmp[5]" merged to single register "ExpWave:u8|d[9]", power-up level changed
Info: Duplicate registers merged to single register
    Info: Duplicate register "ExpWave:u8|tmp[1]" merged to single register "sanjiaobo:u7|l[1]"
    Info: Duplicate register "ExpWave:u8|tmp[2]" merged to single register "sanjiaobo:u7|l[2]"
    Info: Duplicate register "ExpWave:u8|tmp[3]" merged to single register "sanjiaobo:u7|l[3]"
    Info: Duplicate register "ExpWave:u8|tmp[4]" merged to single register "sanjiaobo:u7|l[4]"
Warning: Latch fptd:u4|a[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[0]
Warning: Latch fptd:u4|a[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[0]
Warning: Latch fptd:u4|a[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[2]
Warning: Latch fptd:u4|a[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[1]
Warning: Latch fptd:u4|a[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[0]
Warning: Latch fptd:u4|a[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[0]
Warning: Latch fptd:u4|a[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[1]
Warning: Latch fptd:u4|a[8] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[0]
Warning: Latch fptd:u4|a[9] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[0]
Warning: Latch fptd:u4|a[10] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal td1[1]
Info: Implemented 999 device resources after synthesis - the final resource count might be different
    Info: Implemented 19 input pins
    Info: Implemented 4 output pins
    Info: Implemented 976 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 39 warnings
    Info: Processing ended: Wed Dec 05 15:17:31 2007
    Info: Elapsed time: 00:00:51