fsq.map.rpt

很精典的一个分频程序

; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 976     ;
; Total combinational functions     ; 722     ;
;     -- Total 4-input functions    ; 222     ;
;     -- Total 3-input functions    ; 97      ;
;     -- Total 2-input functions    ; 39      ;
;     -- Total 1-input functions    ; 364     ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 600     ;
; Total logic cells in carry chains ; 366     ;
; I/O pins                          ; 23      ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 249     ;
; Total fan-out                     ; 3276    ;
; Average fan-out                   ; 3.28    ;
+-----------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                      ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |fsq                       ; 976 (0)     ; 600          ; 0          ; 23   ; 0            ; 376 (0)      ; 254 (0)           ; 346 (0)          ; 366 (0)         ; |fsq                ;
;    |ExpWave:u8|            ; 37 (37)     ; 9            ; 0          ; 0    ; 0            ; 28 (28)      ; 1 (1)             ; 8 (8)            ; 0 (0)           ; |fsq|ExpWave:u8     ;
;    |da_tran:u11|           ; 47 (47)     ; 35           ; 0          ; 0    ; 0            ; 12 (12)      ; 2 (2)             ; 33 (33)          ; 32 (32)         ; |fsq|da_tran:u11    ;
;    |fp1:u1|                ; 81 (81)     ; 33           ; 0          ; 0    ; 0            ; 48 (48)      ; 27 (27)           ; 6 (6)            ; 32 (32)         ; |fsq|fp1:u1         ;
;    |fp2:u2|                ; 79 (79)     ; 33           ; 0          ; 0    ; 0            ; 46 (46)      ; 27 (27)           ; 6 (6)            ; 32 (32)         ; |fsq|fp2:u2         ;
;    |fptd:u4|               ; 46 (46)     ; 13           ; 0          ; 0    ; 0            ; 33 (33)      ; 2 (2)             ; 11 (11)          ; 11 (11)         ; |fsq|fptd:u4        ;
;    |mp:u10|                ; 97 (97)     ; 42           ; 0          ; 0    ; 0            ; 55 (55)      ; 1 (1)             ; 41 (41)          ; 32 (32)         ; |fsq|mp:u10         ;
;    |piso:u12|              ; 11 (11)     ; 11           ; 0          ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 10 (10)          ; 0 (0)           ; |fsq|piso:u12       ;
;    |sanjiaobo:u7|          ; 54 (54)     ; 15           ; 0          ; 0    ; 0            ; 39 (39)      ; 0 (0)             ; 15 (15)          ; 35 (35)         ; |fsq|sanjiaobo:u7   ;
;    |timer:u3|              ; 461 (461)   ; 391          ; 0          ; 0    ; 0            ; 70 (70)      ; 192 (192)         ; 199 (199)        ; 192 (192)       ; |fsq|timer:u3       ;
;    |xb:u9|                 ; 34 (34)     ; 9            ; 0          ; 0    ; 0            ; 25 (25)      ; 0 (0)             ; 9 (9)            ; 0 (0)           ; |fsq|xb:u9          ;
;    |zhengxuan:u5|          ; 29 (29)     ; 9            ; 0          ; 0    ; 0            ; 20 (20)      ; 1 (1)             ; 8 (8)            ; 0 (0)           ; |fsq|zhengxuan:u5   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------+
; User-Specified and Inferred Latches                ;
+-----------------------------------------------+----+
; Latch Name                                    ;    ;
+-----------------------------------------------+----+
; fptd:u4|a[1]                                  ;    ;
; fptd:u4|a[2]                                  ;    ;
; fptd:u4|a[3]                                  ;    ;
; fptd:u4|a[4]                                  ;    ;
; fptd:u4|a[5]                                  ;    ;
; fptd:u4|a[6]                                  ;    ;
; fptd:u4|a[7]                                  ;    ;
; fptd:u4|a[8]                                  ;    ;
; fptd:u4|a[9]                                  ;    ;
; fptd:u4|a[10]                                 ;    ;
; Number of user-specified and inferred latches ; 10 ;
+-----------------------------------------------+----+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 600   ;
; Number of registers using Synchronous Clear  ; 233   ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 214   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |fsq|xb:u9|outp[4]         ;
; 3:1                ; 11 bits   ; 22 LEs        ; 0 LEs                ; 22 LEs                 ; Yes        ; |fsq|fptd:u4|\label2:c[0]  ;
; 4:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |fsq|sanjiaobo:u7|q[0]     ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |fsq|sanjiaobo:u7|q[7]     ;
; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; No         ; |fsq|xb:u9|outp4[3]        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/Administrator/桌面/fsq12/fsq12/fsq.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Dec 05 15:16:41 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fsq -c fsq
Info: Found 2 design units, including 1 entities, in source file fangbo.vhd
    Info: Found design unit 1: fangbo-rtl
    Info: Found entity 1: fangbo
Info: Found 2 design units, including 1 entities, in source file sanjiaobo.vhd
    Info: Found design unit 1: sanjiaobo-rtl
    Info: Found entity 1: sanjiaobo
Info: Found 2 design units, including 1 entities, in source file zhengxuan.vhd
    Info: Found design unit 1: zhengxuan-rtl
    Info: Found entity 1: zhengxuan
Warning: Can't analyze file -- file C:/Documents and Settings/Administrator/桌面/fsq12/fsq12/fp.vhd is missing
Warning: Can't analyze file -- file C:/Documents and Settings/Administrator/桌面/fsq12/fsq12/td.vhd is missing
Info: Found 2 design units, including 1 entities, in source file fsq.vhd
    Info: Found design unit 1: fsq-rtl
    Info: Found entity 1: fsq
Info: Found 2 design units, including 1 entities, in source file xb.vhd
    Info: Found design unit 1: xb-rtl
    Info: Found entity 1: xb
Info: Found 2 design units, including 1 entities, in source file da_tran.vhd
    Info: Found design unit 1: da_tran-rtl
    Info: Found entity 1: da_tran
Info: Found 2 design units, including 1 entities, in source file piso.vhd
    Info: Found design unit 1: piso-trl
    Info: Found entity 1: piso
Info: Found 2 design units, including 1 entities, in source file fptd.vhd