mp.vhd

很精典的一个分频程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mp is--脉频
	
port (clk:in std_logic;
      
      mp1:in std_logic_vector(3 downto 0);
      mk:in std_logic_vector(1 downto 0);
      data_in:in std_logic_vector(9 downto 0);
	data_out:out std_logic_vector(9 downto 0));
end mp;
architecture rtl of mp is
signal counter1,ldout,ldout1: integer;
signal waveout:std_logic_vector(9 downto 0);
begin
process(clk)
begin
if (clk'event and clk='1')then
   if counter1=ldout  then
      counter1<=0;
   else 
       counter1<=counter1+1;
   end if;
   if counter1<ldout1 then
      waveout<="1111111111";
   else
      waveout<="0000000000";
   end if;
end if;
end process;
process(mp1)
begin
case mp1 is
when"0000"=>ldout<=39;
when"0001"=>ldout<=49;
when"0010"=>ldout<=59;
when"0011"=>ldout<=69;
when"0100"=>ldout<=79;
when"0101"=>ldout<=89;
when"0110"=>ldout<=99;
when"0111"=>ldout<=119;
when others=>ldout<=39;
end case;
end process;
process(mk)--脉宽
begin
case mk is
when"00"=>ldout1<=5;
when"01"=>ldout1<=10;
when"10"=>ldout1<=20;
when"11"=>ldout1<=30;
when others=>ldout1<=5;
end case;
end process;

process(clk)
begin
if(clk'event and clk='1') then
 data_out<=data_in and waveout;
end if;
end process;

end rtl;