📄 expwave.vhd
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--指数波模块
library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ExpWave is
port(clk : in std_logic;
outp: out std_logic_vector(9 downto 0));
end ExpWave;
architecture Exp_arc of ExpWave is
signal d:integer;
begin
outp<=conv_std_logic_vector(d,10);
process(clk)
variable tmp:integer range 0 to 63;
begin
if clk'event and clk='1' then
if tmp=63 then
tmp:=0;
else
tmp:=tmp+ 1;
end if;
case tmp is
when 00=>d<=1023; when 01=>d<=990; when 02=>d<=959;
when 03=>d<=930; when 04=>d<=903; when 05=>d<=878;
when 06=>d<=855; when 07=>d<=832; when 08=>d<=812;
when 09=>d<=792; when 10=>d<=774; when 11=>d<=757;
when 12=>d<=742; when 13=>d<=727; when 14=>d<=713;
when 15=>d<=700; when 16=>d<=688; when 17=>d<=677;
when 18=>d<=666; when 19=>d<=656; when 20=>d<=647;
when 21=>d<=638; when 22=>d<=630; when 23=>d<=622;
when 24=>d<=615; when 25=>d<=609; when 26=>d<=602;
when 27=>d<=597; when 28=>d<=591; when 29=>d<=586;
when 30=>d<=581; when 31=>d<=577; when 32=>d<=1;
when 33=>d<=34; when 34=>d<=65; when 35=>d<=94;
when 36=>d<=121; when 37=>d<=146; when 38=>d<=170;
when 39=>d<=192; when 40=>d<=212; when 41=>d<=232;
when 42=>d<=250; when 43=>d<=267; when 44=>d<=282;
when 45=>d<=297; when 46=>d<=311; when 47=>d<=324;
when 48=>d<=336; when 49=>d<=348; when 50=>d<=358;
when 51=>d<=368; when 52=>d<=377; when 53=>d<=386;
when 54=>d<=394; when 55=>d<=402; when 56=>d<=409;
when 57=>d<=416; when 58=>d<=422; when 59=>d<=428;
when 60=>d<=433; when 61=>d<=438; when 62=>d<=443;
when 63=>d<=447;
when others=>null;
end case;
end if;
end process;
end Exp_arc;
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