da_tran.vhd

来自「波形发生器之疏密波的产生」· VHDL 代码 · 共 62 行

--D/A时序模块,产生控制D/A芯片的时序cs,dsclk
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY da_tran IS
PORT(rst:in std_logic;--fptd的输出时钟,与波形发生器的输入时钟相同
     clk:in STD_LOGIC;--系统时钟
     cs,dsclk: out STD_LOGIC);
END da_tran;

architecture rtl of da_tran is
signal count:integer;
signal counter:integer;
signal clk1:std_logic;
begin

process(clk)--系统时钟
begin 
	if(clk'event and clk='1') then
	if(count=3)then
		count<=0;
	else	
		count<=count+1;
		if (count<2) then
			clk1<='0';
		else
			clk1<='1';
		end if;
	end if;
	end if;
	dsclk<=clk1;
end process;

process(rst,clk1)
variable counter1:integer;
begin

if (clk1'event and clk1='1') then
if (rst='1')then

   counter1:=counter1+1;

else
   counter1:=0;
end if;
end if;
counter<=counter1;
end process;


process(rst,counter)
begin

if counter<12 and rst='1' then
  cs<='0';
else
  cs<='1';
end if;
end process;
end rtl;