shumi.tan.qmsg

波形发生器之疏密波的产生

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK 32 " "Warning: Circuit may not operate. Detected 32 non-operational path(s) clocked by clock \"CLK\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "fp:inst4\|outp da_tran:inst5\|lpm_counter:counter1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] CLK 500 ps " "Info: Found hold time violation between source  pin or register \"fp:inst4\|outp\" and destination pin or register \"da_tran:inst5\|lpm_counter:counter1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]\" for clock \"CLK\" (Hold time is 500 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.700 ns + Largest " "Info: + Largest clock skew is 5.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.600 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 46 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 46; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "" { CLK } "NODE_NAME" } "" } } { "shumi.bdf" "" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 128 -208 -40 144 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns da_tran:inst5\|clk1 2 REG LC1_C6 46 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_C6; Fanout = 46; REG Node = 'da_tran:inst5\|clk1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "2.500 ns" { CLK da_tran:inst5|clk1 } "NODE_NAME" } "" } } { "da_tran.vhd" "" { Text "D:/altera/qdesigns51/shumi/da_tran.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.000 ns) 7.600 ns da_tran:inst5\|lpm_counter:counter1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 3 REG LC5_C37 3 " "Info: 3: + IC(4.600 ns) + CELL(0.000 ns) = 7.600 ns; Loc. = LC5_C37; Fanout = 3; REG Node = 'da_tran:inst5\|lpm_counter:counter1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "4.600 ns" { da_tran:inst5|clk1 da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 21.05 % ) " "Info: Total cell delay = 1.600 ns ( 21.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns ( 78.95 % ) " "Info: Total interconnect delay = 6.000 ns ( 78.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "7.600 ns" { CLK da_tran:inst5|clk1 da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { CLK CLK~out da_tran:inst5|clk1 da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 1.400ns 4.600ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.900 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 46 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 46; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "" { CLK } "NODE_NAME" } "" } } { "shumi.bdf" "" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 128 -208 -40 144 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns fp:inst4\|outp 2 REG LC6_A37 72 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC6_A37; Fanout = 72; REG Node = 'fp:inst4\|outp'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "1.400 ns" { CLK fp:inst4|outp } "NODE_NAME" } "" } } { "fp.vhd" "" { Text "D:/altera/qdesigns51/shumi/fp.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "1.900 ns" { CLK fp:inst4|outp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out fp:inst4|outp } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "7.600 ns" { CLK da_tran:inst5|clk1 da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { CLK CLK~out da_tran:inst5|clk1 da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 1.400ns 4.600ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "1.900 ns" { CLK fp:inst4|outp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out fp:inst4|outp } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "fp.vhd" "" { Text "D:/altera/qdesigns51/shumi/fp.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.000 ns - Shortest register register " "Info: - Shortest register to register delay is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fp:inst4\|outp 1 REG LC6_A37 72 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A37; Fanout = 72; REG Node = 'fp:inst4\|outp'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "" { fp:inst4|outp } "NODE_NAME" } "" } } { "fp.vhd" "" { Text "D:/altera/qdesigns51/shumi/fp.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(1.300 ns) 5.000 ns da_tran:inst5\|lpm_counter:counter1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 2 REG LC5_C37 3 " "Info: 2: + IC(3.700 ns) + CELL(1.300 ns) = 5.000 ns; Loc. = LC5_C37; Fanout = 3; REG Node = 'da_tran:inst5\|lpm_counter:counter1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "5.000 ns" { fp:inst4|outp da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns ( 26.00 % ) " "Info: Total cell delay = 1.300 ns ( 26.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.700 ns ( 74.00 % ) " "Info: Total interconnect delay = 3.700 ns ( 74.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "5.000 ns" { fp:inst4|outp da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.000 ns" { fp:inst4|outp da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 3.700ns } { 0.000ns 1.300ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.900 ns + " "Info: + Micro hold delay of destination is 0.900 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "7.600 ns" { CLK da_tran:inst5|clk1 da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { CLK CLK~out da_tran:inst5|clk1 da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 1.400ns 4.600ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "1.900 ns" { CLK fp:inst4|outp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out fp:inst4|outp } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "5.000 ns" { fp:inst4|outp da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.000 ns" { fp:inst4|outp da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 3.700ns } { 0.000ns 1.300ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "xb:inst6\|outp3\[8\] K M 6.800 ns register " "Info: tsu for register \"xb:inst6\|outp3\[8\]\" (data pin = \"K\", clock pin = \"M\") is 6.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.300 ns + Longest pin register " "Info: + Longest pin to register delay is 14.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns K 1 CLK PIN_93 4 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_93; Fanout = 4; CLK Node = 'K'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "" { K } "NODE_NAME" } "" } } { "shumi.bdf" "" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 176 408 576 192 "K" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.700 ns) + CELL(2.200 ns) 10.000 ns xb:inst6\|Mux~131 2 COMB LC7_C29 1 " "Info: 2: + IC(4.700 ns) + CELL(2.200 ns) = 10.000 ns; Loc. = LC7_C29; Fanout = 1; COMB Node = 'xb:inst6\|Mux~131'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "6.900 ns" { K xb:inst6|Mux~131 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 12.100 ns xb:inst6\|Mux~132 3 COMB LC8_C29 1 " "Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 12.100 ns; Loc. = LC8_C29; Fanout = 1; COMB Node = 'xb:inst6\|Mux~132'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "2.100 ns" { xb:inst6|Mux~131 xb:inst6|Mux~132 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 14.300 ns xb:inst6\|outp3\[8\] 4 REG LC2_C29 5 " "Info: 4: + IC(0.200 ns) + CELL(2.000 ns) = 14.300 ns; Loc. = LC2_C29; Fanout = 5; REG Node = 'xb:inst6\|outp3\[8\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "2.200 ns" { xb:inst6|Mux~132 xb:inst6|outp3[8] } "NODE_NAME" } "" } } { "xb.vhd" "" { Text "D:/altera/qdesigns51/shumi/xb.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.200 ns ( 64.34 % ) " "Info: Total cell delay = 9.200 ns ( 64.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.100 ns ( 35.66 % ) " "Info: Total interconnect delay = 5.100 ns ( 35.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "14.300 ns" { K xb:inst6|Mux~131 xb:inst6|Mux~132 xb:inst6|outp3[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.300 ns" { K K~out xb:inst6|Mux~131 xb:inst6|Mux~132 xb:inst6|outp3[8] } { 0.000ns 0.000ns 4.700ns 0.200ns 0.200ns } { 0.000ns 3.100ns 2.200ns 1.900ns 2.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.800 ns + " "Info: + Micro setup delay of destination is 3.800 ns" {  } { { "xb.vhd" "" { Text "D:/altera/qdesigns51/shumi/xb.vhd" 37 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "M destination 11.300 ns - Shortest register " "Info: - Shortest clock path from clock \"M\" to destination register is 11.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns M 1 CLK PIN_90 1 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_90; Fanout = 1; CLK Node = 'M'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "" { M } "NODE_NAME" } "" } } { "shumi.bdf" "" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 144 408 576 160 "M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(1.700 ns) 9.400 ns xb:inst6\|Mux~130 2 COMB LC6_C29 2 " "Info: 2: + IC(4.600 ns) + CELL(1.700 ns) = 9.400 ns; Loc. = LC6_C29; Fanout = 2; COMB Node = 'xb:inst6\|Mux~130'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "6.300 ns" { M xb:inst6|Mux~130 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 11.300 ns xb:inst6\|outp3\[8\] 3 REG LC2_C29 5 " "Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 11.300 ns; Loc. = LC2_C29; Fanout = 5; REG Node = 'xb:inst6\|outp3\[8\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "1.900 ns" { xb:inst6|Mux~130 xb:inst6|outp3[8] } "NODE_NAME" } "" } } { "xb.vhd" "" { Text "D:/altera/qdesigns51/shumi/xb.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.500 ns ( 57.52 % ) " "Info: Total cell delay = 6.500 ns ( 57.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.800 ns ( 42.48 % ) " "Info: Total interconnect delay = 4.800 ns ( 42.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "11.300 ns" { M xb:inst6|Mux~130 xb:inst6|outp3[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.300 ns" { M M~out xb:inst6|Mux~130 xb:inst6|outp3[8] } { 0.000ns 0.000ns 4.600ns 0.200ns } { 0.000ns 3.100ns 1.700ns 1.700ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "14.300 ns" { K xb:inst6|Mux~131 xb:inst6|Mux~132 xb:inst6|outp3[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.300 ns" { K K~out xb:inst6|Mux~131 xb:inst6|Mux~132 xb:inst6|outp3[8] } { 0.000ns 0.000ns 4.700ns 0.200ns 0.200ns } { 0.000ns 3.100ns 2.200ns 1.900ns 2.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "11.300 ns" { M xb:inst6|Mux~130 xb:inst6|outp3[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.300 ns" { M M~out xb:inst6|Mux~130 xb:inst6|outp3[8] } { 0.000ns 0.000ns 4.600ns 0.200ns } { 0.000ns 3.100ns 1.700ns 1.700ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}