📄 shumi.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "shumi.bdf" "" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 128 -208 -40 144 "CLK" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "N " "Info: Assuming node \"N\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "shumi.bdf" "" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 160 408 576 176 "N" "" } } } } } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "K " "Info: Assuming node \"K\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "shumi.bdf" "" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 176 408 576 192 "K" "" } } } } } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "M " "Info: Assuming node \"M\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "shumi.bdf" "" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 144 408 576 160 "M" "" } } } } } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "xb:inst6\|Mux~130 " "Info: Detected gated clock \"xb:inst6\|Mux~130\" as buffer" { } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "xb:inst6\|Mux~130" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "da_tran:inst5\|clk1 " "Info: Detected ripple clock \"da_tran:inst5\|clk1\" as buffer" { } { { "da_tran.vhd" "" { Text "D:/altera/qdesigns51/shumi/da_tran.vhd" 21 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "da_tran:inst5\|clk1" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fp:inst4\|outp " "Info: Detected ripple clock \"fp:inst4\|outp\" as buffer" { } { { "fp.vhd" "" { Text "D:/altera/qdesigns51/shumi/fp.vhd" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fp:inst4\|outp" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register da_tran:inst5\|lpm_counter:counter1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[13\] register piso:inst7\|tmp\[10\] 30.67 MHz 32.6 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 30.67 MHz between source register \"da_tran:inst5\|lpm_counter:counter1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[13\]\" and destination register \"piso:inst7\|tmp\[10\]\" (period= 32.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.500 ns + Longest register register " "Info: + Longest register to register delay is 14.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns da_tran:inst5\|lpm_counter:counter1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[13\] 1 REG LC6_C39 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_C39; Fanout = 3; REG Node = 'da_tran:inst5\|lpm_counter:counter1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[13\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "" { da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[13] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.500 ns) 2.600 ns da_tran:inst5\|process2~334 2 COMB LC3_C40 1 " "Info: 2: + IC(1.100 ns) + CELL(1.500 ns) = 2.600 ns; Loc. = LC3_C40; Fanout = 1; COMB Node = 'da_tran:inst5\|process2~334'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "2.600 ns" { da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[13] da_tran:inst5|process2~334 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 4.500 ns da_tran:inst5\|process2~321 3 COMB LC4_C40 1 " "Info: 3: + IC(0.000 ns) + CELL(1.900 ns) = 4.500 ns; Loc. = LC4_C40; Fanout = 1; COMB Node = 'da_tran:inst5\|process2~321'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "1.900 ns" { da_tran:inst5|process2~334 da_tran:inst5|process2~321 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.200 ns) 6.900 ns da_tran:inst5\|process2~307 4 COMB LC6_C40 1 " "Info: 4: + IC(0.200 ns) + CELL(2.200 ns) = 6.900 ns; Loc. = LC6_C40; Fanout = 1; COMB Node = 'da_tran:inst5\|process2~307'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "2.400 ns" { da_tran:inst5|process2~321 da_tran:inst5|process2~307 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 8.800 ns da_tran:inst5\|process2~308 5 COMB LC1_C40 2 " "Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 8.800 ns; Loc. = LC1_C40; Fanout = 2; COMB Node = 'da_tran:inst5\|process2~308'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "1.900 ns" { da_tran:inst5|process2~307 da_tran:inst5|process2~308 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.000 ns) 11.900 ns da_tran:inst5\|process2~309 6 COMB LC8_C44 11 " "Info: 6: + IC(1.100 ns) + CELL(2.000 ns) = 11.900 ns; Loc. = LC8_C44; Fanout = 11; COMB Node = 'da_tran:inst5\|process2~309'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "3.100 ns" { da_tran:inst5|process2~308 da_tran:inst5|process2~309 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.500 ns) 14.500 ns piso:inst7\|tmp\[10\] 7 REG LC3_C51 1 " "Info: 7: + IC(1.100 ns) + CELL(1.500 ns) = 14.500 ns; Loc. = LC3_C51; Fanout = 1; REG Node = 'piso:inst7\|tmp\[10\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "2.600 ns" { da_tran:inst5|process2~309 piso:inst7|tmp[10] } "NODE_NAME" } "" } } { "piso.vhd" "" { Text "D:/altera/qdesigns51/shumi/piso.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.800 ns ( 74.48 % ) " "Info: Total cell delay = 10.800 ns ( 74.48 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.700 ns ( 25.52 % ) " "Info: Total interconnect delay = 3.700 ns ( 25.52 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "14.500 ns" { da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[13] da_tran:inst5|process2~334 da_tran:inst5|process2~321 da_tran:inst5|process2~307 da_tran:inst5|process2~308 da_tran:inst5|process2~309 piso:inst7|tmp[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.500 ns" { da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[13] da_tran:inst5|process2~334 da_tran:inst5|process2~321 da_tran:inst5|process2~307 da_tran:inst5|process2~308 da_tran:inst5|process2~309 piso:inst7|tmp[10] } { 0.000ns 1.100ns 0.000ns 0.200ns 0.200ns 1.100ns 1.100ns } { 0.000ns 1.500ns 1.900ns 2.200ns 1.700ns 2.000ns 1.500ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.600 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 46 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 46; CLK Node = 'CLK'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "" { CLK } "NODE_NAME" } "" } } { "shumi.bdf" "" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 128 -208 -40 144 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns da_tran:inst5\|clk1 2 REG LC1_C6 46 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_C6; Fanout = 46; REG Node = 'da_tran:inst5\|clk1'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "2.500 ns" { CLK da_tran:inst5|clk1 } "NODE_NAME" } "" } } { "da_tran.vhd" "" { Text "D:/altera/qdesigns51/shumi/da_tran.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.000 ns) 7.600 ns piso:inst7\|tmp\[10\] 3 REG LC3_C51 1 " "Info: 3: + IC(4.600 ns) + CELL(0.000 ns) = 7.600 ns; Loc. = LC3_C51; Fanout = 1; REG Node = 'piso:inst7\|tmp\[10\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "4.600 ns" { da_tran:inst5|clk1 piso:inst7|tmp[10] } "NODE_NAME" } "" } } { "piso.vhd" "" { Text "D:/altera/qdesigns51/shumi/piso.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 21.05 % ) " "Info: Total cell delay = 1.600 ns ( 21.05 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns ( 78.95 % ) " "Info: Total interconnect delay = 6.000 ns ( 78.95 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "7.600 ns" { CLK da_tran:inst5|clk1 piso:inst7|tmp[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { CLK CLK~out da_tran:inst5|clk1 piso:inst7|tmp[10] } { 0.000ns 0.000ns 1.400ns 4.600ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.600 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 46 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 46; CLK Node = 'CLK'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "" { CLK } "NODE_NAME" } "" } } { "shumi.bdf" "" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 128 -208 -40 144 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns da_tran:inst5\|clk1 2 REG LC1_C6 46 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_C6; Fanout = 46; REG Node = 'da_tran:inst5\|clk1'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "2.500 ns" { CLK da_tran:inst5|clk1 } "NODE_NAME" } "" } } { "da_tran.vhd" "" { Text "D:/altera/qdesigns51/shumi/da_tran.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.000 ns) 7.600 ns da_tran:inst5\|lpm_counter:counter1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[13\] 3 REG LC6_C39 3 " "Info: 3: + IC(4.600 ns) + CELL(0.000 ns) = 7.600 ns; Loc. = LC6_C39; Fanout = 3; REG Node = 'da_tran:inst5\|lpm_counter:counter1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[13\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "4.600 ns" { da_tran:inst5|clk1 da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[13] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 21.05 % ) " "Info: Total cell delay = 1.600 ns ( 21.05 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns ( 78.95 % ) " "Info: Total interconnect delay = 6.000 ns ( 78.95 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "7.600 ns" { CLK da_tran:inst5|clk1 da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { CLK CLK~out da_tran:inst5|clk1 da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[13] } { 0.000ns 0.000ns 1.400ns 4.600ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "7.600 ns" { CLK da_tran:inst5|clk1 piso:inst7|tmp[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { CLK CLK~out da_tran:inst5|clk1 piso:inst7|tmp[10] } { 0.000ns 0.000ns 1.400ns 4.600ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "7.600 ns" { CLK da_tran:inst5|clk1 da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { CLK CLK~out da_tran:inst5|clk1 da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[13] } { 0.000ns 0.000ns 1.400ns 4.600ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" { } { { "piso.vhd" "" { Text "D:/altera/qdesigns51/shumi/piso.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } { "piso.vhd" "" { Text "D:/altera/qdesigns51/shumi/piso.vhd" 17 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "14.500 ns" { da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[13] da_tran:inst5|process2~334 da_tran:inst5|process2~321 da_tran:inst5|process2~307 da_tran:inst5|process2~308 da_tran:inst5|process2~309 piso:inst7|tmp[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.500 ns" { da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[13] da_tran:inst5|process2~334 da_tran:inst5|process2~321 da_tran:inst5|process2~307 da_tran:inst5|process2~308 da_tran:inst5|process2~309 piso:inst7|tmp[10] } { 0.000ns 1.100ns 0.000ns 0.200ns 0.200ns 1.100ns 1.100ns } { 0.000ns 1.500ns 1.900ns 2.200ns 1.700ns 2.000ns 1.500ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "7.600 ns" { CLK da_tran:inst5|clk1 piso:inst7|tmp[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { CLK CLK~out da_tran:inst5|clk1 piso:inst7|tmp[10] } { 0.000ns 0.000ns 1.400ns 4.600ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shumi" "UNKNOWN" "V1" "D:/altera/qdesigns51/shumi/db/shumi.quartus_db" { Floorplan "D:/altera/qdesigns51/shumi/" "" "7.600 ns" { CLK da_tran:inst5|clk1 da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { CLK CLK~out da_tran:inst5|clk1 da_tran:inst5|lpm_counter:counter1_rtl_0|alt_counter_f10ke:wysi_counter|q[13] } { 0.000ns 0.000ns 1.400ns 4.600ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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