shumi.map.qmsg

波形发生器之疏密波的产生

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "piso piso:inst7 " "Info: Elaborating entity \"piso\" for hierarchy \"piso:inst7\"" {  } { { "shumi.bdf" "inst7" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 536 584 680 632 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "xb xb:inst6 " "Info: Elaborating entity \"xb\" for hierarchy \"xb:inst6\"" {  } { { "shumi.bdf" "inst6" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 104 584 720 296 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "outp2 xb.vhd(20) " "Info (10035): Verilog HDL or VHDL information at xb.vhd(20): object \"outp2\" declared but not used" {  } { { "xb.vhd" "" { Text "D:/altera/qdesigns51/shumi/xb.vhd" 20 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "wave xb.vhd(22) " "Info (10035): Verilog HDL or VHDL information at xb.vhd(22): object \"wave\" declared but not used" {  } { { "xb.vhd" "" { Text "D:/altera/qdesigns51/shumi/xb.vhd" 22 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "outp1 xb.vhd(33) " "Warning (10492): VHDL Process Statement warning at xb.vhd(33): signal \"outp1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xb.vhd" "" { Text "D:/altera/qdesigns51/shumi/xb.vhd" 33 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q0 xb.vhd(40) " "Warning (10492): VHDL Process Statement warning at xb.vhd(40): signal \"q0\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xb.vhd" "" { Text "D:/altera/qdesigns51/shumi/xb.vhd" 40 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q1 xb.vhd(41) " "Warning (10492): VHDL Process Statement warning at xb.vhd(41): signal \"q1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xb.vhd" "" { Text "D:/altera/qdesigns51/shumi/xb.vhd" 41 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q2 xb.vhd(42) " "Warning (10492): VHDL Process Statement warning at xb.vhd(42): signal \"q2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xb.vhd" "" { Text "D:/altera/qdesigns51/shumi/xb.vhd" 42 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q3 xb.vhd(43) " "Warning (10492): VHDL Process Statement warning at xb.vhd(43): signal \"q3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xb.vhd" "" { Text "D:/altera/qdesigns51/shumi/xb.vhd" 43 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "outp3 xb.vhd(47) " "Warning (10492): VHDL Process Statement warning at xb.vhd(47): signal \"outp3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xb.vhd" "" { Text "D:/altera/qdesigns51/shumi/xb.vhd" 47 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "chui chui:inst " "Info: Elaborating entity \"chui\" for hierarchy \"chui:inst\"" {  } { { "shumi.bdf" "inst" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 104 168 280 200 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "chui.vhd(87) " "Info (10425): VHDL Case Statement information at chui.vhd(87): OTHERS choice is never selected" {  } { { "chui.vhd" "" { Text "D:/altera/qdesigns51/shumi/chui.vhd" 87 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jiu jiu:inst1 " "Info: Elaborating entity \"jiu\" for hierarchy \"jiu:inst1\"" {  } { { "shumi.bdf" "inst1" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 216 168 280 312 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "jiu.vhd(87) " "Info (10425): VHDL Case Statement information at jiu.vhd(87): OTHERS choice is never selected" {  } { { "jiu.vhd" "" { Text "D:/altera/qdesigns51/shumi/jiu.vhd" 87 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rou rou:inst2 " "Info: Elaborating entity \"rou\" for hierarchy \"rou:inst2\"" {  } { { "shumi.bdf" "inst2" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 328 168 280 424 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "rou.vhd(87) " "Info (10425): VHDL Case Statement information at rou.vhd(87): OTHERS choice is never selected" {  } { { "rou.vhd" "" { Text "D:/altera/qdesigns51/shumi/rou.vhd" 87 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "duanxu duanxu:inst8 " "Info: Elaborating entity \"duanxu\" for hierarchy \"duanxu:inst8\"" {  } { { "shumi.bdf" "inst8" { Schematic "D:/altera/qdesigns51/shumi/shumi.bdf" { { 440 168 280 536 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "duanxu.vhd(87) " "Info (10425): VHDL Case Statement information at duanxu.vhd(87): OTHERS choice is never selected" {  } { { "duanxu.vhd" "" { Text "D:/altera/qdesigns51/shumi/duanxu.vhd" 87 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}