shumi.map.rpt

波形发生器之疏密波的产生

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; Analysis & Synthesis Equations ;
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The equations can be found in D:/altera/qdesigns51/shumi/shumi.map.eqn.


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; Analysis & Synthesis Messages ;
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Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri May 16 20:46:08 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shumi -c shumi
Info: Found 2 design units, including 1 entities, in source file square.vhd
    Info: Found design unit 1: square-rtl
    Info: Found entity 1: square
Warning: Can't analyze file -- file D:/altera/qdesigns51/shumi/shu.vhd is missing
Info: Found 2 design units, including 1 entities, in source file rou.vhd
    Info: Found design unit 1: rou-rtl
    Info: Found entity 1: rou
Info: Found 2 design units, including 1 entities, in source file jiu.vhd
    Info: Found design unit 1: jiu-rtl
    Info: Found entity 1: jiu
Info: Found 2 design units, including 1 entities, in source file chui.vhd
    Info: Found design unit 1: chui-rtl
    Info: Found entity 1: chui
Info: Found 1 design units, including 1 entities, in source file shumi.bdf
    Info: Found entity 1: shumi
Info: Found 2 design units, including 1 entities, in source file fp.vhd
    Info: Found design unit 1: fp-rtl
    Info: Found entity 1: fp
Info: Found 2 design units, including 1 entities, in source file da_tran.vhd
    Info: Found design unit 1: da_tran-rtl
    Info: Found entity 1: da_tran
Info: Found 2 design units, including 1 entities, in source file xb.vhd
    Info: Found design unit 1: xb-rtl
    Info: Found entity 1: xb
Info: Found 2 design units, including 1 entities, in source file piso.vhd
    Info: Found design unit 1: piso-trl
    Info: Found entity 1: piso
Info: Found 2 design units, including 1 entities, in source file duanxu.vhd
    Info: Found design unit 1: duanxu-rtl
    Info: Found entity 1: duanxu
Info: Elaborating entity "shumi" for the top level hierarchy
Info: Elaborating entity "da_tran" for hierarchy "da_tran:inst5"
Warning (10492): VHDL Process Statement warning at da_tran.vhd(33): signal "clk1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "fp" for hierarchy "fp:inst4"
Info: Elaborating entity "piso" for hierarchy "piso:inst7"
Info: Elaborating entity "xb" for hierarchy "xb:inst6"
Info (10035): Verilog HDL or VHDL information at xb.vhd(20): object "outp2" declared but not used
Info (10035): Verilog HDL or VHDL information at xb.vhd(22): object "wave" declared but not used
Warning (10492): VHDL Process Statement warning at xb.vhd(33): signal "outp1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at xb.vhd(40): signal "q0" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at xb.vhd(41): signal "q1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at xb.vhd(42): signal "q2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at xb.vhd(43): signal "q3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at xb.vhd(47): signal "outp3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "chui" for hierarchy "chui:inst"
Info (10425): VHDL Case Statement information at chui.vhd(87): OTHERS choice is never selected
Info: Elaborating entity "jiu" for hierarchy "jiu:inst1"
Info (10425): VHDL Case Statement information at jiu.vhd(87): OTHERS choice is never selected
Info: Elaborating entity "rou" for hierarchy "rou:inst2"
Info (10425): VHDL Case Statement information at rou.vhd(87): OTHERS choice is never selected
Info: Elaborating entity "duanxu" for hierarchy "duanxu:inst8"
Info (10425): VHDL Case Statement information at duanxu.vhd(87): OTHERS choice is never selected
Warning: Reduced register "piso:inst7|tmp[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "piso:inst7|tmp[1]" with stuck data_in port to stuck value GND
Info: Inferred 5 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "da_tran:inst5|counter1[0]~32"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: "duanxu:inst8|tmp[0]~0"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: "chui:inst|tmp[0]~0"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: "jiu:inst1|tmp[0]~0"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: "rou:inst2|tmp[0]~0"
Info: Found 1 design units, including 1 entities, in source file ../../quartus51/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file ../../quartus51/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units, including 1 entities, in source file ../../quartus51/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file ../../quartus51/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file ../../quartus51/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file ../../quartus51/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Duplicate registers merged to single register
    Info: Duplicate register "duanxu:inst8|data[8]" merged to single register "duanxu:inst8|data[9]"
    Info: Duplicate register "duanxu:inst8|data[7]" merged to single register "duanxu:inst8|data[9]"
    Info: Duplicate register "duanxu:inst8|data[6]" merged to single register "duanxu:inst8|data[9]"
    Info: Duplicate register "duanxu:inst8|data[5]" merged to single register "duanxu:inst8|data[9]"
    Info: Duplicate register "duanxu:inst8|data[4]" merged to single register "duanxu:inst8|data[9]"
    Info: Duplicate register "duanxu:inst8|data[3]" merged to single register "duanxu:inst8|data[9]"
    Info: Duplicate register "duanxu:inst8|data[2]" merged to single register "duanxu:inst8|data[9]"
    Info: Duplicate register "duanxu:inst8|data[1]" merged to single register "duanxu:inst8|data[9]"
    Info: Duplicate register "duanxu:inst8|data[0]" merged to single register "duanxu:inst8|data[9]"
    Info: Duplicate register "chui:inst|data[8]" merged to single register "chui:inst|data[9]"
    Info: Duplicate register "chui:inst|data[7]" merged to single register "chui:inst|data[9]"
    Info: Duplicate register "chui:inst|data[6]" merged to single register "chui:inst|data[9]"
    Info: Duplicate register "chui:inst|data[5]" merged to single register "chui:inst|data[9]"
    Info: Duplicate register "chui:inst|data[4]" merged to single register "chui:inst|data[9]"
    Info: Duplicate register "chui:inst|data[3]" merged to single register "chui:inst|data[9]"
    Info: Duplicate register "chui:inst|data[2]" merged to single register "chui:inst|data[9]"
    Info: Duplicate register "chui:inst|data[1]" merged to single register "chui:inst|data[9]"
    Info: Duplicate register "chui:inst|data[0]" merged to single register "chui:inst|data[9]"
    Info: Duplicate register "jiu:inst1|data[8]" merged to single register "jiu:inst1|data[9]"
    Info: Duplicate register "jiu:inst1|data[7]" merged to single register "jiu:inst1|data[9]"
    Info: Duplicate register "jiu:inst1|data[6]" merged to single register "jiu:inst1|data[9]"
    Info: Duplicate register "jiu:inst1|data[5]" merged to single register "jiu:inst1|data[9]"
    Info: Duplicate register "jiu:inst1|data[4]" merged to single register "jiu:inst1|data[9]"
    Info: Duplicate register "jiu:inst1|data[3]" merged to single register "jiu:inst1|data[9]"
    Info: Duplicate register "jiu:inst1|data[2]" merged to single register "jiu:inst1|data[9]"
    Info: Duplicate register "jiu:inst1|data[1]" merged to single register "jiu:inst1|data[9]"
    Info: Duplicate register "jiu:inst1|data[0]" merged to single register "jiu:inst1|data[9]"
    Info: Duplicate register "rou:inst2|data[8]" merged to single register "rou:inst2|data[9]"
    Info: Duplicate register "rou:inst2|data[7]" merged to single register "rou:inst2|data[9]"
    Info: Duplicate register "rou:inst2|data[6]" merged to single register "rou:inst2|data[9]"
    Info: Duplicate register "rou:inst2|data[5]" merged to single register "rou:inst2|data[9]"
    Info: Duplicate register "rou:inst2|data[4]" merged to single register "rou:inst2|data[9]"
    Info: Duplicate register "rou:inst2|data[3]" merged to single register "rou:inst2|data[9]"
    Info: Duplicate register "rou:inst2|data[2]" merged to single register "rou:inst2|data[9]"
    Info: Duplicate register "rou:inst2|data[1]" merged to single register "rou:inst2|data[9]"
    Info: Duplicate register "rou:inst2|data[0]" merged to single register "rou:inst2|data[9]"
Info: Duplicate LATCH primitives merged into single LATCH primitive
    Info: Duplicate LATCH primitive "xb:inst6|outp3[7]" merged with LATCH primitive "xb:inst6|outp3[9]"
    Info: Duplicate LATCH primitive "xb:inst6|outp3[5]" merged with LATCH primitive "xb:inst6|outp3[9]"
    Info: Duplicate LATCH primitive "xb:inst6|outp3[3]" merged with LATCH primitive "xb:inst6|outp3[9]"
    Info: Duplicate LATCH primitive "xb:inst6|outp3[1]" merged with LATCH primitive "xb:inst6|outp3[9]"
    Info: Duplicate LATCH primitive "xb:inst6|outp3[6]" merged with LATCH primitive "xb:inst6|outp3[8]"
    Info: Duplicate LATCH primitive "xb:inst6|outp3[4]" merged with LATCH primitive "xb:inst6|outp3[8]"
    Info: Duplicate LATCH primitive "xb:inst6|outp3[2]" merged with LATCH primitive "xb:inst6|outp3[8]"
    Info: Duplicate LATCH primitive "xb:inst6|outp3[0]" merged with LATCH primitive "xb:inst6|outp3[8]"
Warning: Latch xb:inst6|outp3[9] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal N
Warning: Latch xb:inst6|outp3[8] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal K
Info: Implemented 209 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 3 output pins
    Info: Implemented 201 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings
    Info: Processing ended: Fri May 16 20:46:35 2008
    Info: Elapsed time: 00:00:30