square.vhd

波形发生器之疏密波的产生

--方波发生模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY square IS
PORT(clk:IN STD_LOGIC;
     outp:out integer range 0 to 1023);
END square;

ARCHITECTURE rtl OF square IS
  signal tmp:integer range 63 downto 0;
begin

process(clk)
begin
  if(clk'event and clk='1') then
       tmp<=tmp+1;
    if tmp>31 then
       outp<=1023;
    else 
       outp<=0;
    end if;
  end if;
end process;
end rtl;