piano_vhdl.txt

硬件电子琴VHDL设计 硬件电子琴VHDL设计

硬件电子琴VHDL设计
一：notetabs

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity notetabs is

     port(clk:in std_logic;

   xuanze:in std_logic;

          toneindex:out std_logic_vector(3 downto 0));

end;

architecture one of notetabs is

component music

   port(address:in std_logic_vector(8 downto 0);

        inclock:in std_logic;

         q:out std_logic_vector(3 downto 0));

 end component;

    signal counter:std_logic_vector(8 downto 0);

  begin

cnt8:process(clk)

  begin

if(clk'event and clk='1')then 

case counter is

when "010001011"=>if xuanze='1' then counter<="010001100";

else counter<="000000000";end if;

when "111010110"=>if xuanze='1' then counter<="000000000";

else counter<="010001100";end if;

when others=>counter<=counter+1;

end case;end if;

end process;

u1:music port map(address=>counter,q=>toneindex,inclock=>clk);

end;

 

二：tonetaba

library ieee;

use ieee.std_logic_1164.all;

entity tonetaba is

port (index:in std_logic_vector(3 downto 0);

      code:out std_logic_vector(3 downto 0);

      high:out std_logic;

      tone:out std_logic_vector(9 downto 0));

end;

architecture one of tonetaba is

begin

  search:process(index)

  begin

     case index is

  when "0000"=>tone<="1111111111";code<="0000";high<='0';--1023

  when "0001"=>tone<="1000100011";code<="0001";high<='0';--547;

  when "0010"=>tone<="1001010111";code<="0010";high<='0';--599; 

  when "0011"=>tone<="1010000110";code<="0011";high<='0';--646;

  when "0100"=>tone<="1010011010";code<="0100";high<='0';--666;

  when "0101"=>tone<="1011000010";code<="0101";high<='0';--706;

  when "0110"=>tone<="1011100100";code<="0110";high<='0';--740;

  when "0111"=>tone<="1100000011";code<="0111";high<='0';--771;

  when "1000"=>tone<="1100010010";code<="0001";high<='1';--786;

  when "1001"=>tone<="1100101100";code<="0010";high<='1';--812;

  when "1010"=>tone<="1101000011";code<="0011";high<='1';--835;

  when "1011"=>tone<="1101001101";code<="0100";high<='1';--845;

  when "1100"=>tone<="1101100001";code<="0101";high<='1';--865;

  when "1101"=>tone<="1101110010";code<="0110";high<='1';--882;

  when "1110"=>tone<="1110000001";code<="0111";high<='1';--897; 

  when "1111"=>tone<="1110001000";code<="1000";high<='1';--905;  

when others=>null;

  end case;

end process;

end;

 

三：speakera

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity speakera is

     port(clk:in std_logic;

          tone:in std_logic_vector(9 downto 0 );

          spks:out std_logic);

end;

architecture one of speakera is

    signal fullspks:std_logic;

 begin

process(clk,tone)

   variable count10:std_logic_vector(9 downto 0);

begin

if clk'event and clk='1' then

      if count10=1023 then count10:=tone;fullspks<='1';

          else count10:=count10+1;fullspks<='0';

       end if;

    end if;

end process;

dalayspks:process(fullspks)

    variable count2:std_logic;

begin

  if fullspks'event and fullspks='1'then count2:=not count2;

     if count2='1'then spks<='1';

     else spks<='0';

     end if;

  end if;

end process;

end;

 

四：顶层文件设计

library ieee;

use ieee.std_logic_1164.all;

entity songer is

   port (clk250khz:in std_logic; 

     xuanze1:in std_logic;                    

         clk4HZ:in std_logic; 

         code1:out std_logic_vector(3 downto 0); 

         high1:out std_logic;                         

         spkout :out std_logic); 

   end ;

architecture one of songer is

  component notetabs

   port(clk:in std_logic;

xuan:in std_logic;

        toneindex:out std_logic_vector(3 downto 0));

   end component;

  component tonetaba

   port(index:in std_logic_vector(3 downto 0);

        code:out std_logic_vector(3 downto 0);

        high:out std_logic;

        tone:out std_logic_vector(9 downto 0));

   end component;

  component speakera

   port(clk:in std_logic;

         tone:in std_logic_vector(9 downto 0);

         spks:out std_logic);

  end component;

  signal tone:std_logic_vector(9 downto 0);

  signal toneindex:std_logic_vector(3 downto 0);

 begin

u1:notetabs port map(clk=>clk4HZ,xuanze=>xuanze1,toneindex=>toneindex);

u2:tonetaba port map(index=>toneindex,tone=>tone,code=>code1,high=>high1);

u3:speakera port map(clk=>clk250khz,tone=>tone,spks=>spkout);

  end;