wb_conbusex_top_bench.v

wb_conbus设计源代码,需要的下载可以

		.s8_ack_i(	s8_ack_i	),
		.s8_err_i(	s8_err_i	),
		.s8_rty_i(	s8_rty_i	),
		.s8_cab_o(	s8_cab_o	),
		.s9_dat_i(	s9_dat_i	),
		.s9_dat_o(	s9_dat_o	),
		.s9_adr_o(	s9_adr_o	),
		.s9_sel_o(	s9_sel_o	),
		.s9_we_o(	s9_we_o		),
		.s9_cyc_o(	s9_cyc_o	),
		.s9_stb_o(	s9_stb_o	),
		.s9_ack_i(	s9_ack_i	),
		.s9_err_i(	s9_err_i	),
		.s9_rty_i(	s9_rty_i	),
		.s9_cab_o(	s9_cab_o	),
		.s10_dat_i(	s10_dat_i	),
		.s10_dat_o(	s10_dat_o	),
		.s10_adr_o(	s10_adr_o	),
		.s10_sel_o(	s10_sel_o	),
		.s10_we_o(	s10_we_o	),
		.s10_cyc_o(	s10_cyc_o	),
		.s10_stb_o(	s10_stb_o	),
		.s10_ack_i(	s10_ack_i	),
		.s10_err_i(	s10_err_i	),
		.s10_rty_i(	s10_rty_i	),
		.s10_cab_o(	s10_cab_o	),
		.s11_dat_i(	s11_dat_i	),
		.s11_dat_o(	s11_dat_o	),
		.s11_adr_o(	s11_adr_o	),
		.s11_sel_o(	s11_sel_o	),
		.s11_we_o(	s11_we_o	),
		.s11_cyc_o(	s11_cyc_o	),
		.s11_stb_o(	s11_stb_o	),
		.s11_ack_i(	s11_ack_i	),
		.s11_err_i(	s11_err_i	),
		.s11_rty_i(	s11_rty_i	),
		.s11_cab_o(	s11_cab_o	),
		.s12_dat_i(	s12_dat_i	),
		.s12_dat_o(	s12_dat_o	),
		.s12_adr_o(	s12_adr_o	),
		.s12_sel_o(	s12_sel_o	),
		.s12_we_o(	s12_we_o	),
		.s12_cyc_o(	s12_cyc_o	),
		.s12_stb_o(	s12_stb_o	),
		.s12_ack_i(	s12_ack_i	),
		.s12_err_i(	s12_err_i	),
		.s12_rty_i(	s12_rty_i	),
		.s12_cab_o(	s12_cab_o	),
		.s13_dat_i(	s13_dat_i	),
		.s13_dat_o(	s13_dat_o	),
		.s13_adr_o(	s13_adr_o	),
		.s13_sel_o(	s13_sel_o	),
		.s13_we_o(	s13_we_o	),
		.s13_cyc_o(	s13_cyc_o	),
		.s13_stb_o(	s13_stb_o	),
		.s13_ack_i(	s13_ack_i	),
		.s13_err_i(	s13_err_i	),
		.s13_rty_i(	s13_rty_i	),
		.s13_cab_o(	s13_cab_o	),
		.s14_dat_i(	s14_dat_i	),
		.s14_dat_o(	s14_dat_o	),
		.s14_adr_o(	s14_adr_o	),
		.s14_sel_o(	s14_sel_o	),
		.s14_we_o(	s14_we_o	),
		.s14_cyc_o(	s14_cyc_o	),
		.s14_stb_o(	s14_stb_o	),
		.s14_ack_i(	s14_ack_i	),
		.s14_err_i(	s14_err_i	),
		.s14_rty_i(	s14_rty_i	),
		.s14_cab_o(	s14_cab_o	),
		.s15_dat_i(	s15_dat_i	),
		.s15_dat_o(	s15_dat_o	),
		.s15_adr_o(	s15_adr_o	),
		.s15_sel_o(	s15_sel_o	),
		.s15_we_o(	s15_we_o	),
		.s15_cyc_o(	s15_cyc_o	),
		.s15_stb_o(	s15_stb_o	),
		.s15_ack_i(	s15_ack_i	),
		.s15_err_i(	s15_err_i	),
		.s15_rty_i(	s15_rty_i	),
		.s15_cab_o(	s15_cab_o	)
		);


/////////////////////////////////////////////////////////////////////
//
// WISHBONE Master Models
//

wb_mast	m0(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		m0_adr_i	),
		.din(		m0_dat_o	),
		.dout(		m0_dat_i	),
		.cyc(		m0_cyc_i	),
		.stb(		m0_stb_i	),
		.sel(		m0_sel_i	),
		.we(		m0_we_i		),
		.ack(		m0_ack_o	),
		.err(		m0_err_o	),
		.rty(		m0_rty_o	)
		);

wb_mast	m1(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		m1_adr_i	),
		.din(		m1_dat_o	),
		.dout(		m1_dat_i	),
		.cyc(		m1_cyc_i	),
		.stb(		m1_stb_i	),
		.sel(		m1_sel_i	),
		.we(		m1_we_i		),
		.ack(		m1_ack_o	),
		.err(		m1_err_o	),
		.rty(		m1_rty_o	)
		);

wb_mast	m2(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		m2_adr_i	),
		.din(		m2_dat_o	),
		.dout(		m2_dat_i	),
		.cyc(		m2_cyc_i	),
		.stb(		m2_stb_i	),
		.sel(		m2_sel_i	),
		.we(		m2_we_i		),
		.ack(		m2_ack_o	),
		.err(		m2_err_o	),
		.rty(		m2_rty_o	)
		);

wb_mast	m3(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		m3_adr_i	),
		.din(		m3_dat_o	),
		.dout(		m3_dat_i	),
		.cyc(		m3_cyc_i	),
		.stb(		m3_stb_i	),
		.sel(		m3_sel_i	),
		.we(		m3_we_i		),
		.ack(		m3_ack_o	),
		.err(		m3_err_o	),
		.rty(		m3_rty_o	)
		);

wb_mast	m4(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		m4_adr_i	),
		.din(		m4_dat_o	),
		.dout(		m4_dat_i	),
		.cyc(		m4_cyc_i	),
		.stb(		m4_stb_i	),
		.sel(		m4_sel_i	),
		.we(		m4_we_i		),
		.ack(		m4_ack_o	),
		.err(		m4_err_o	),
		.rty(		m4_rty_o	)
		);

wb_mast	m5(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		m5_adr_i	),
		.din(		m5_dat_o	),
		.dout(		m5_dat_i	),
		.cyc(		m5_cyc_i	),
		.stb(		m5_stb_i	),
		.sel(		m5_sel_i	),
		.we(		m5_we_i		),
		.ack(		m5_ack_o	),
		.err(		m5_err_o	),
		.rty(		m5_rty_o	)
		);

wb_mast	m6(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		m6_adr_i	),
		.din(		m6_dat_o	),
		.dout(		m6_dat_i	),
		.cyc(		m6_cyc_i	),
		.stb(		m6_stb_i	),
		.sel(		m6_sel_i	),
		.we(		m6_we_i		),
		.ack(		m6_ack_o	),
		.err(		m6_err_o	),
		.rty(		m6_rty_o	)
		);

wb_mast	m7(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		m7_adr_i	),
		.din(		m7_dat_o	),
		.dout(		m7_dat_i	),
		.cyc(		m7_cyc_i	),
		.stb(		m7_stb_i	),
		.sel(		m7_sel_i	),
		.we(		m7_we_i		),
		.ack(		m7_ack_o	),
		.err(		m7_err_o	),
		.rty(		m7_rty_o	)
		);


/////////////////////////////////////////////////////////////////////
//
// WISHBONE Slave Models
//

wb_slv  s0(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s0_adr_o	),
		.din(		s0_dat_o	),
		.dout(		s0_dat_i	),
		.cyc(		s0_cyc_o	),
		.stb(		s0_stb_o	),
		.sel(		s0_sel_o	),
		.we(		s0_we_o		),
		.ack(		s0_ack_i	),
		.err(		s0_err_i	),
		.rty(		s0_rty_i	)
		);

wb_slv  s1(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s1_adr_o	),
		.din(		s1_dat_o	),
		.dout(		s1_dat_i	),
		.cyc(		s1_cyc_o	),
		.stb(		s1_stb_o	),
		.sel(		s1_sel_o	),
		.we(		s1_we_o		),
		.ack(		s1_ack_i	),
		.err(		s1_err_i	),
		.rty(		s1_rty_i	)
		);

wb_slv  s2(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s2_adr_o	),
		.din(		s2_dat_o	),
		.dout(		s2_dat_i	),
		.cyc(		s2_cyc_o	),
		.stb(		s2_stb_o	),
		.sel(		s2_sel_o	),
		.we(		s2_we_o		),
		.ack(		s2_ack_i	),
		.err(		s2_err_i	),
		.rty(		s2_rty_i	)
		);

wb_slv  s3(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s3_adr_o	),
		.din(		s3_dat_o	),
		.dout(		s3_dat_i	),
		.cyc(		s3_cyc_o	),
		.stb(		s3_stb_o	),
		.sel(		s3_sel_o	),
		.we(		s3_we_o		),
		.ack(		s3_ack_i	),
		.err(		s3_err_i	),
		.rty(		s3_rty_i	)
		);

wb_slv  s4(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s4_adr_o	),
		.din(		s4_dat_o	),
		.dout(		s4_dat_i	),
		.cyc(		s4_cyc_o	),
		.stb(		s4_stb_o	),
		.sel(		s4_sel_o	),
		.we(		s4_we_o		),
		.ack(		s4_ack_i	),
		.err(		s4_err_i	),
		.rty(		s4_rty_i	)
		);

wb_slv  s5(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s5_adr_o	),
		.din(		s5_dat_o	),
		.dout(		s5_dat_i	),
		.cyc(		s5_cyc_o	),
		.stb(		s5_stb_o	),
		.sel(		s5_sel_o	),
		.we(		s5_we_o		),
		.ack(		s5_ack_i	),
		.err(		s5_err_i	),
		.rty(		s5_rty_i	)
		);

wb_slv  s6(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s6_adr_o	),
		.din(		s6_dat_o	),
		.dout(		s6_dat_i	),
		.cyc(		s6_cyc_o	),
		.stb(		s6_stb_o	),
		.sel(		s6_sel_o	),
		.we(		s6_we_o		),
		.ack(		s6_ack_i	),
		.err(		s6_err_i	),
		.rty(		s6_rty_i	)
		);

wb_slv  s7(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s7_adr_o	),
		.din(		s7_dat_o	),
		.dout(		s7_dat_i	),
		.cyc(		s7_cyc_o	),
		.stb(		s7_stb_o	),
		.sel(		s7_sel_o	),
		.we(		s7_we_o		),
		.ack(		s7_ack_i	),
		.err(		s7_err_i	),
		.rty(		s7_rty_i	)
		);

wb_slv  s8(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s8_adr_o	),
		.din(		s8_dat_o	),
		.dout(		s8_dat_i	),
		.cyc(		s8_cyc_o	),
		.stb(		s8_stb_o	),
		.sel(		s8_sel_o	),
		.we(		s8_we_o		),
		.ack(		s8_ack_i	),
		.err(		s8_err_i	),
		.rty(		s8_rty_i	)
		);

wb_slv  s9(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s9_adr_o	),
		.din(		s9_dat_o	),
		.dout(		s9_dat_i	),
		.cyc(		s9_cyc_o	),
		.stb(		s9_stb_o	),
		.sel(		s9_sel_o	),
		.we(		s9_we_o		),
		.ack(		s9_ack_i	),
		.err(		s9_err_i	),
		.rty(		s9_rty_i	)
		);

wb_slv  s10(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s10_adr_o	),
		.din(		s10_dat_o	),
		.dout(		s10_dat_i	),
		.cyc(		s10_cyc_o	),
		.stb(		s10_stb_o	),
		.sel(		s10_sel_o	),
		.we(		s10_we_o	),
		.ack(		s10_ack_i	),
		.err(		s10_err_i	),
		.rty(		s10_rty_i	)
		);

wb_slv  s11(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s11_adr_o	),
		.din(		s11_dat_o	),
		.dout(		s11_dat_i	),
		.cyc(		s11_cyc_o	),
		.stb(		s11_stb_o	),
		.sel(		s11_sel_o	),
		.we(		s11_we_o	),
		.ack(		s11_ack_i	),
		.err(		s11_err_i	),
		.rty(		s11_rty_i	)
		);

wb_slv  s12(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s12_adr_o	),
		.din(		s12_dat_o	),
		.dout(		s12_dat_i	),
		.cyc(		s12_cyc_o	),
		.stb(		s12_stb_o	),
		.sel(		s12_sel_o	),
		.we(		s12_we_o	),
		.ack(		s12_ack_i	),
		.err(		s12_err_i	),
		.rty(		s12_rty_i	)
		);

wb_slv  s13(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s13_adr_o	),
		.din(		s13_dat_o	),
		.dout(		s13_dat_i	),
		.cyc(		s13_cyc_o	),
		.stb(		s13_stb_o	),
		.sel(		s13_sel_o	),
		.we(		s13_we_o	),
		.ack(		s13_ack_i	),
		.err(		s13_err_i	),
		.rty(		s13_rty_i	)
		);

wb_slv  s14(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s14_adr_o	),
		.din(		s14_dat_o	),
		.dout(		s14_dat_i	),
		.cyc(		s14_cyc_o	),
		.stb(		s14_stb_o	),
		.sel(		s14_sel_o	),
		.we(		s14_we_o	),
		.ack(		s14_ack_i	),
		.err(		s14_err_i	),
		.rty(		s14_rty_i	)
		);

wb_slv  s15(	.clk(		clk		),
		.rst(		~rst		),
		.adr(		s15_adr_o	),
		.din(		s15_dat_o	),
		.dout(		s15_dat_i	),
		.cyc(		s15_cyc_o	),
		.stb(		s15_stb_o	),
		.sel(		s15_sel_o	),
		.we(		s15_we_o	),
		.ack(		s15_ack_i	),
		.err(		s15_err_i	),
		.rty(		s15_rty_i	)
		);

reg	[31:0]	rdata[0:15];

/////////////////////////////////////////////////////////////////////
//
// Simulation Initialization and Start up Section
//
initial
   begin

	$display("\n\n");
	$display("*****************************************************");
	$display("* WISHBONE Connection Matrix Simulation started ... *");
	$display("*****************************************************");
	$display("\n");

   	clk = 1;
   	rst = 1;

   	repeat(5)	@(posedge clk);
	s0.delay = 1;
	s1.delay = 1;
	s2.delay = 1;
	s3.delay = 1;
	s4.delay = 1;
	s5.delay = 1;
	s6.delay = 1;
	s7.delay = 1;
	s8.delay = 1;
	s9.delay = 1;
	s10.delay = 1;
	s11.delay = 1;
	s12.delay = 1;
	s13.delay = 1;
	s14.delay = 1;
	s15.delay = 1;
	init_all_mem;
	#1;
	rst = 0;
	repeat(5)	@(posedge clk);

	m0.wb_wr1(32'h0000_0000, 4'hf, 32'h01234567);
	m0.wb_rd1(32'h0000_0000, 4'hf, rdata[0]);
	
	m0.wb_wr4(32'h0000_0010, 4'hf, 0, 32'h01010101, 32'h02020202, 32'h03030303, 32'h04040404);
	m0.wb_rd4(32'h0000_0010, 4'hf, 0, rdata[4], rdata[5], rdata[6], rdata[7]);

	m1.wb_wr1(32'h9000_0000, 4'hf, 32'h01234567);
	m1.wb_rd1(32'h9000_0000, 4'hf, rdata[8]);
	
	m1.wb_wr4(32'h9000_0010, 4'hf, 0, 32'h05050505, 32'h06060606, 32'h07070707, 32'h08080808);
	m1.wb_rd4(32'h9000_0010, 4'hf, 0, rdata[12], rdata[13], rdata[14], rdata[15]);
	
	repeat(5)	@(posedge clk);
	$stop;
end	// End of Initial

/////////////////////////////////////////////////////////////////////
//
// Clock Generation
//

always #5	clk = ~clk;

task init_all_mem;
begin
	s0.fill_mem(1);
	s1.fill_mem(1);
	s2.fill_mem(1);
	s3.fill_mem(1);
	s4.fill_mem(1);
	s5.fill_mem(1);
	s6.fill_mem(1);
	s7.fill_mem(1);
	s8.fill_mem(1);
	s9.fill_mem(1);
	s10.fill_mem(1);
	s11.fill_mem(1);
	s12.fill_mem(1);
	s13.fill_mem(1);
	s14.fill_mem(1);
	s15.fill_mem(1);
	m0.mem_fill;
	m1.mem_fill;
	m2.mem_fill;
	m3.mem_fill;
	m4.mem_fill;
	m5.mem_fill;
	m6.mem_fill;
	m7.mem_fill;
end
endtask


endmodule