wb_conbusex_top_bench.v

wb_conbus设计源代码,需要的下载可以

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Top Level Test Bench                                       ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          [e-mail]                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         [e-mail]                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

//  CVS Log
//
//  $Id: test_bench_top.v,v 1.2 2002/10/03 05:40:03 rudi Exp $
//
//  $Date: 2002/10/03 05:40:03 $
//  $Revision: 1.2 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: test_bench_top.v,v $
//               Revision 1.2  2002/10/03 05:40:03  rudi
//               Fixed a minor bug in parameter passing, updated headers and specification.
//
//               Revision 1.1.1.1  2001/10/19 11:04:25  rudi
//               WISHBONE CONMAX IP Core
//
//
//
//
//
//


`include "timescale.v"

module wb_conbusex_top_bench;

reg		clk;
reg		rst;

// IO Prototypes
wire	[31:0]	m0_dat_i;
wire	[31:0]	m0_dat_o;
wire	[31:0]	m0_adr_i;
wire	[3:0]	m0_sel_i;
wire		m0_we_i;
wire		m0_cyc_i;
wire		m0_stb_i;
wire		m0_cab_i = 1'b0;
wire		m0_ack_o;
wire		m0_err_o;
wire		m0_rty_o;
wire	[31:0]	m1_dat_i;
wire	[31:0]	m1_dat_o;
wire	[31:0]	m1_adr_i;
wire	[3:0]	m1_sel_i;
wire		m1_we_i;
wire		m1_cyc_i;
wire		m1_stb_i;
wire		m1_cab_i = 1'b0;
wire		m1_ack_o;
wire		m1_err_o;
wire		m1_rty_o;
wire	[31:0]	m2_dat_i;
wire	[31:0]	m2_dat_o;
wire	[31:0]	m2_adr_i;
wire	[3:0]	m2_sel_i;
wire		m2_we_i;
wire		m2_cyc_i;
wire		m2_stb_i;
wire		m2_cab_i = 1'b0;
wire		m2_ack_o;
wire		m2_err_o;
wire		m2_rty_o;
wire	[31:0]	m3_dat_i;
wire	[31:0]	m3_dat_o;
wire	[31:0]	m3_adr_i;
wire	[3:0]	m3_sel_i;
wire		m3_we_i;
wire		m3_cyc_i;
wire		m3_stb_i;
wire		m3_cab_i = 1'b0;
wire		m3_ack_o;
wire		m3_err_o;
wire		m3_rty_o;
wire	[31:0]	m4_dat_i;
wire	[31:0]	m4_dat_o;
wire	[31:0]	m4_adr_i;
wire	[3:0]	m4_sel_i;
wire		m4_we_i;
wire		m4_cyc_i;
wire		m4_stb_i;
wire		m4_cab_i = 1'b0;
wire		m4_ack_o;
wire		m4_err_o;
wire		m4_rty_o;
wire	[31:0]	m5_dat_i;
wire	[31:0]	m5_dat_o;
wire	[31:0]	m5_adr_i;
wire	[3:0]	m5_sel_i;
wire		m5_we_i;
wire		m5_cyc_i;
wire		m5_stb_i;
wire		m5_cab_i = 1'b0;
wire		m5_ack_o;
wire		m5_err_o;
wire		m5_rty_o;
wire	[31:0]	m6_dat_i;
wire	[31:0]	m6_dat_o;
wire	[31:0]	m6_adr_i;
wire	[3:0]	m6_sel_i;
wire		m6_we_i;
wire		m6_cyc_i;
wire		m6_stb_i;
wire		m6_cab_i = 1'b0;
wire		m6_ack_o;
wire		m6_err_o;
wire		m6_rty_o;
wire	[31:0]	m7_dat_i;
wire	[31:0]	m7_dat_o;
wire	[31:0]	m7_adr_i;
wire	[3:0]	m7_sel_i;
wire		m7_we_i;
wire		m7_cyc_i;
wire		m7_stb_i;
wire		m7_cab_i = 1'b0;
wire		m7_ack_o;
wire		m7_err_o;
wire		m7_rty_o;
wire	[31:0]	s0_dat_i;
wire	[31:0]	s0_dat_o;
wire	[31:0]	s0_adr_o;
wire	[3:0]	s0_sel_o;
wire		s0_we_o;
wire		s0_cyc_o;
wire		s0_stb_o;
wire		s0_cab_o;
wire		s0_ack_i;
wire		s0_err_i;
wire		s0_rty_i;
wire	[31:0]	s1_dat_i;
wire	[31:0]	s1_dat_o;
wire	[31:0]	s1_adr_o;
wire	[3:0]	s1_sel_o;
wire		s1_we_o;
wire		s1_cyc_o;
wire		s1_stb_o;
wire		s1_cab_o;
wire		s1_ack_i;
wire		s1_err_i;
wire		s1_rty_i;
wire	[31:0]	s2_dat_i;
wire	[31:0]	s2_dat_o;
wire	[31:0]	s2_adr_o;
wire	[3:0]	s2_sel_o;
wire		s2_we_o;
wire		s2_cyc_o;
wire		s2_stb_o;
wire		s2_cab_o;
wire		s2_ack_i;
wire		s2_err_i;
wire		s2_rty_i;
wire	[31:0]	s3_dat_i;
wire	[31:0]	s3_dat_o;
wire	[31:0]	s3_adr_o;
wire	[3:0]	s3_sel_o;
wire		s3_we_o;
wire		s3_cyc_o;
wire		s3_stb_o;
wire		s3_cab_o;
wire		s3_ack_i;
wire		s3_err_i;
wire		s3_rty_i;
wire	[31:0]	s4_dat_i;
wire	[31:0]	s4_dat_o;
wire	[31:0]	s4_adr_o;
wire	[3:0]	s4_sel_o;
wire		s4_we_o;
wire		s4_cyc_o;
wire		s4_stb_o;
wire		s4_cab_o;
wire		s4_ack_i;
wire		s4_err_i;
wire		s4_rty_i;
wire	[31:0]	s5_dat_i;
wire	[31:0]	s5_dat_o;
wire	[31:0]	s5_adr_o;
wire	[3:0]	s5_sel_o;
wire		s5_we_o;
wire		s5_cyc_o;
wire		s5_stb_o;
wire		s5_cab_o;
wire		s5_ack_i;
wire		s5_err_i;
wire		s5_rty_i;
wire	[31:0]	s6_dat_i;
wire	[31:0]	s6_dat_o;
wire	[31:0]	s6_adr_o;
wire	[3:0]	s6_sel_o;
wire		s6_we_o;
wire		s6_cyc_o;
wire		s6_stb_o;
wire		s6_cab_o;
wire		s6_ack_i;
wire		s6_err_i;
wire		s6_rty_i;
wire	[31:0]	s7_dat_i;
wire	[31:0]	s7_dat_o;
wire	[31:0]	s7_adr_o;
wire	[3:0]	s7_sel_o;
wire		s7_we_o;
wire		s7_cyc_o;
wire		s7_stb_o;
wire		s7_cab_o;
wire		s7_ack_i;
wire		s7_err_i;
wire		s7_rty_i;
wire	[31:0]	s8_dat_i;
wire	[31:0]	s8_dat_o;
wire	[31:0]	s8_adr_o;
wire	[3:0]	s8_sel_o;
wire		s8_we_o;
wire		s8_cyc_o;
wire		s8_stb_o;
wire		s8_cab_o;
wire		s8_ack_i;
wire		s8_err_i;
wire		s8_rty_i;
wire	[31:0]	s9_dat_i;
wire	[31:0]	s9_dat_o;
wire	[31:0]	s9_adr_o;
wire	[3:0]	s9_sel_o;
wire		s9_we_o;
wire		s9_cyc_o;
wire		s9_stb_o;
wire		s9_cab_o;
wire		s9_ack_i;
wire		s9_err_i;
wire		s9_rty_i;
wire	[31:0]	s10_dat_i;
wire	[31:0]	s10_dat_o;
wire	[31:0]	s10_adr_o;
wire	[3:0]	s10_sel_o;
wire		s10_we_o;
wire		s10_cyc_o;
wire		s10_stb_o;
wire		s10_cab_o;
wire		s10_ack_i;
wire		s10_err_i;
wire		s10_rty_i;
wire	[31:0]	s11_dat_i;
wire	[31:0]	s11_dat_o;
wire	[31:0]	s11_adr_o;
wire	[3:0]	s11_sel_o;
wire		s11_we_o;
wire		s11_cyc_o;
wire		s11_stb_o;
wire		s11_cab_o;
wire		s11_ack_i;
wire		s11_err_i;
wire		s11_rty_i;
wire	[31:0]	s12_dat_i;
wire	[31:0]	s12_dat_o;
wire	[31:0]	s12_adr_o;
wire	[3:0]	s12_sel_o;
wire		s12_we_o;
wire		s12_cyc_o;
wire		s12_stb_o;
wire		s12_cab_o;
wire		s12_ack_i;
wire		s12_err_i;
wire		s12_rty_i;
wire	[31:0]	s13_dat_i;
wire	[31:0]	s13_dat_o;
wire	[31:0]	s13_adr_o;
wire	[3:0]	s13_sel_o;
wire		s13_we_o;
wire		s13_cyc_o;
wire		s13_stb_o;
wire		s13_cab_o;
wire		s13_ack_i;
wire		s13_err_i;
wire		s13_rty_i;
wire	[31:0]	s14_dat_i;
wire	[31:0]	s14_dat_o;
wire	[31:0]	s14_adr_o;
wire	[3:0]	s14_sel_o;
wire		s14_we_o;
wire		s14_cyc_o;
wire		s14_stb_o;
wire		s14_cab_o;
wire		s14_ack_i;
wire		s14_err_i;
wire		s14_rty_i;
wire	[31:0]	s15_dat_i;
wire	[31:0]	s15_dat_o;
wire	[31:0]	s15_adr_o;
wire	[3:0]	s15_sel_o;
wire		s15_we_o;
wire		s15_cyc_o;
wire		s15_stb_o;
wire		s15_cab_o;
wire		s15_ack_i;
wire		s15_err_i;
wire		s15_rty_i;


/////////////////////////////////////////////////////////////////////
//
// WISHBONE Inter Connect
//

wb_conbusex_top	conmax(
		.clk_i(		clk		),
		.rst_i(		rst		),
		.m0_dat_i(	m0_dat_i	),
		.m0_dat_o(	m0_dat_o	),
		.m0_adr_i(	m0_adr_i	),
		.m0_sel_i(	m0_sel_i	),
		.m0_we_i(	m0_we_i		),
		.m0_cyc_i(	m0_cyc_i	),
		.m0_stb_i(	m0_stb_i	),
		.m0_ack_o(	m0_ack_o	),
		.m0_err_o(	m0_err_o	),
		.m0_rty_o(	m0_rty_o	),
		.m0_cab_i(	m0_cab_i	),
		.m1_dat_i(	m1_dat_i	),
		.m1_dat_o(	m1_dat_o	),
		.m1_adr_i(	m1_adr_i	),
		.m1_sel_i(	m1_sel_i	),
		.m1_we_i(	m1_we_i		),
		.m1_cyc_i(	m1_cyc_i	),
		.m1_stb_i(	m1_stb_i	),
		.m1_ack_o(	m1_ack_o	),
		.m1_err_o(	m1_err_o	),
		.m1_rty_o(	m1_rty_o	),
		.m1_cab_i(	m2_cab_i	),
		.m2_dat_i(	m2_dat_i	),
		.m2_dat_o(	m2_dat_o	),
		.m2_adr_i(	m2_adr_i	),
		.m2_sel_i(	m2_sel_i	),
		.m2_we_i(	m2_we_i		),
		.m2_cyc_i(	m2_cyc_i	),
		.m2_stb_i(	m2_stb_i	),
		.m2_ack_o(	m2_ack_o	),
		.m2_err_o(	m2_err_o	),
		.m2_rty_o(	m2_rty_o	),
		.m2_cab_i(	m2_cab_i	),
		.m3_dat_i(	m3_dat_i	),
		.m3_dat_o(	m3_dat_o	),
		.m3_adr_i(	m3_adr_i	),
		.m3_sel_i(	m3_sel_i	),
		.m3_we_i(	m3_we_i		),
		.m3_cyc_i(	m3_cyc_i	),
		.m3_stb_i(	m3_stb_i	),
		.m3_ack_o(	m3_ack_o	),
		.m3_err_o(	m3_err_o	),
		.m3_rty_o(	m3_rty_o	),
		.m3_cab_i(	m3_cab_i	),
		.m4_dat_i(	m4_dat_i	),
		.m4_dat_o(	m4_dat_o	),
		.m4_adr_i(	m4_adr_i	),
		.m4_sel_i(	m4_sel_i	),
		.m4_we_i(	m4_we_i		),
		.m4_cyc_i(	m4_cyc_i	),
		.m4_stb_i(	m4_stb_i	),
		.m4_ack_o(	m4_ack_o	),
		.m4_err_o(	m4_err_o	),
		.m4_rty_o(	m4_rty_o	),
		.m4_cab_i(	m4_cab_i	),
		.m5_dat_i(	m5_dat_i	),
		.m5_dat_o(	m5_dat_o	),
		.m5_adr_i(	m5_adr_i	),
		.m5_sel_i(	m5_sel_i	),
		.m5_we_i(	m5_we_i		),
		.m5_cyc_i(	m5_cyc_i	),
		.m5_stb_i(	m5_stb_i	),
		.m5_ack_o(	m5_ack_o	),
		.m5_err_o(	m5_err_o	),
		.m5_rty_o(	m5_rty_o	),
		.m5_cab_i(	m5_cab_i	),
		.m6_dat_i(	m6_dat_i	),
		.m6_dat_o(	m6_dat_o	),
		.m6_adr_i(	m6_adr_i	),
		.m6_sel_i(	m6_sel_i	),
		.m6_we_i(	m6_we_i		),
		.m6_cyc_i(	m6_cyc_i	),
		.m6_stb_i(	m6_stb_i	),
		.m6_ack_o(	m6_ack_o	),
		.m6_err_o(	m6_err_o	),
		.m6_rty_o(	m6_rty_o	),
		.m6_cab_i(	m6_cab_i	),
		.m7_dat_i(	m7_dat_i	),
		.m7_dat_o(	m7_dat_o	),
		.m7_adr_i(	m7_adr_i	),
		.m7_sel_i(	m7_sel_i	),
		.m7_we_i(	m7_we_i		),
		.m7_cyc_i(	m7_cyc_i	),
		.m7_stb_i(	m7_stb_i	),
		.m7_ack_o(	m7_ack_o	),
		.m7_err_o(	m7_err_o	),
		.m7_rty_o(	m7_rty_o	),
		.m7_cab_i(	m7_cab_i	),
		.s0_dat_i(	s0_dat_i	),
		.s0_dat_o(	s0_dat_o	),
		.s0_adr_o(	s0_adr_o	),
		.s0_sel_o(	s0_sel_o	),
		.s0_we_o(	s0_we_o		),
		.s0_cyc_o(	s0_cyc_o	),
		.s0_stb_o(	s0_stb_o	),
		.s0_ack_i(	s0_ack_i	),
		.s0_err_i(	s0_err_i	),
		.s0_rty_i(	s0_rty_i	),
		.s0_cab_o(	s0_cab_o	),
		.s1_dat_i(	s1_dat_i	),
		.s1_dat_o(	s1_dat_o	),
		.s1_adr_o(	s1_adr_o	),
		.s1_sel_o(	s1_sel_o	),
		.s1_we_o(	s1_we_o		),
		.s1_cyc_o(	s1_cyc_o	),
		.s1_stb_o(	s1_stb_o	),
		.s1_ack_i(	s1_ack_i	),
		.s1_err_i(	s1_err_i	),
		.s1_rty_i(	s1_rty_i	),
		.s1_cab_o(	s1_cab_o	),
		.s2_dat_i(	s2_dat_i	),
		.s2_dat_o(	s2_dat_o	),
		.s2_adr_o(	s2_adr_o	),
		.s2_sel_o(	s2_sel_o	),
		.s2_we_o(	s2_we_o		),
		.s2_cyc_o(	s2_cyc_o	),
		.s2_stb_o(	s2_stb_o	),
		.s2_ack_i(	s2_ack_i	),
		.s2_err_i(	s2_err_i	),
		.s2_rty_i(	s2_rty_i	),
		.s2_cab_o(	s2_cab_o	),
		.s3_dat_i(	s3_dat_i	),
		.s3_dat_o(	s3_dat_o	),
		.s3_adr_o(	s3_adr_o	),
		.s3_sel_o(	s3_sel_o	),
		.s3_we_o(	s3_we_o		),
		.s3_cyc_o(	s3_cyc_o	),
		.s3_stb_o(	s3_stb_o	),
		.s3_ack_i(	s3_ack_i	),
		.s3_err_i(	s3_err_i	),
		.s3_rty_i(	s3_rty_i	),
		.s3_cab_o(	s3_cab_o	),
		.s4_dat_i(	s4_dat_i	),
		.s4_dat_o(	s4_dat_o	),
		.s4_adr_o(	s4_adr_o	),
		.s4_sel_o(	s4_sel_o	),
		.s4_we_o(	s4_we_o		),
		.s4_cyc_o(	s4_cyc_o	),
		.s4_stb_o(	s4_stb_o	),
		.s4_ack_i(	s4_ack_i	),
		.s4_err_i(	s4_err_i	),
		.s4_rty_i(	s4_rty_i	),
		.s4_cab_o(	s4_cab_o	),
		.s5_dat_i(	s5_dat_i	),
		.s5_dat_o(	s5_dat_o	),
		.s5_adr_o(	s5_adr_o	),
		.s5_sel_o(	s5_sel_o	),
		.s5_we_o(	s5_we_o		),
		.s5_cyc_o(	s5_cyc_o	),
		.s5_stb_o(	s5_stb_o	),
		.s5_ack_i(	s5_ack_i	),
		.s5_err_i(	s5_err_i	),
		.s5_rty_i(	s5_rty_i	),
		.s5_cab_o(	s5_cab_o	),
		.s6_dat_i(	s6_dat_i	),
		.s6_dat_o(	s6_dat_o	),
		.s6_adr_o(	s6_adr_o	),
		.s6_sel_o(	s6_sel_o	),
		.s6_we_o(	s6_we_o		),
		.s6_cyc_o(	s6_cyc_o	),
		.s6_stb_o(	s6_stb_o	),
		.s6_ack_i(	s6_ack_i	),
		.s6_err_i(	s6_err_i	),
		.s6_rty_i(	s6_rty_i	),
		.s6_cab_o(	s6_cab_o	),
		.s7_dat_i(	s7_dat_i	),
		.s7_dat_o(	s7_dat_o	),
		.s7_adr_o(	s7_adr_o	),
		.s7_sel_o(	s7_sel_o	),
		.s7_we_o(	s7_we_o		),
		.s7_cyc_o(	s7_cyc_o	),
		.s7_stb_o(	s7_stb_o	),
		.s7_ack_i(	s7_ack_i	),
		.s7_err_i(	s7_err_i	),
		.s7_rty_i(	s7_rty_i	),
		.s7_cab_o(	s7_cab_o	),
		.s8_dat_i(	s8_dat_i	),
		.s8_dat_o(	s8_dat_o	),
		.s8_adr_o(	s8_adr_o	),
		.s8_sel_o(	s8_sel_o	),
		.s8_we_o(	s8_we_o		),
		.s8_cyc_o(	s8_cyc_o	),
		.s8_stb_o(	s8_stb_o	),