📄 wb_conbusex_top.v
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output s0_cyc_o;
output s0_stb_o;
output s0_cab_o;
input s0_ack_i;
input s0_err_i;
input s0_rty_i;
// Slave 1 Interface
input [`dw-1:0] s1_dat_i;
output [`dw-1:0] s1_dat_o;
output [`aw-1:0] s1_adr_o;
output [`sw-1:0] s1_sel_o;
output s1_we_o;
output s1_cyc_o;
output s1_stb_o;
output s1_cab_o;
input s1_ack_i;
input s1_err_i;
input s1_rty_i;
// Slave 2 Interface
input [`dw-1:0] s2_dat_i;
output [`dw-1:0] s2_dat_o;
output [`aw-1:0] s2_adr_o;
output [`sw-1:0] s2_sel_o;
output s2_we_o;
output s2_cyc_o;
output s2_stb_o;
output s2_cab_o;
input s2_ack_i;
input s2_err_i;
input s2_rty_i;
// Slave 3 Interface
input [`dw-1:0] s3_dat_i;
output [`dw-1:0] s3_dat_o;
output [`aw-1:0] s3_adr_o;
output [`sw-1:0] s3_sel_o;
output s3_we_o;
output s3_cyc_o;
output s3_stb_o;
output s3_cab_o;
input s3_ack_i;
input s3_err_i;
input s3_rty_i;
// Slave 4 Interface
input [`dw-1:0] s4_dat_i;
output [`dw-1:0] s4_dat_o;
output [`aw-1:0] s4_adr_o;
output [`sw-1:0] s4_sel_o;
output s4_we_o;
output s4_cyc_o;
output s4_stb_o;
output s4_cab_o;
input s4_ack_i;
input s4_err_i;
input s4_rty_i;
// Slave 5 Interface
input [`dw-1:0] s5_dat_i;
output [`dw-1:0] s5_dat_o;
output [`aw-1:0] s5_adr_o;
output [`sw-1:0] s5_sel_o;
output s5_we_o;
output s5_cyc_o;
output s5_stb_o;
output s5_cab_o;
input s5_ack_i;
input s5_err_i;
input s5_rty_i;
// Slave 6 Interface
input [`dw-1:0] s6_dat_i;
output [`dw-1:0] s6_dat_o;
output [`aw-1:0] s6_adr_o;
output [`sw-1:0] s6_sel_o;
output s6_we_o;
output s6_cyc_o;
output s6_stb_o;
output s6_cab_o;
input s6_ack_i;
input s6_err_i;
input s6_rty_i;
// Slave 7 Interface
input [`dw-1:0] s7_dat_i;
output [`dw-1:0] s7_dat_o;
output [`aw-1:0] s7_adr_o;
output [`sw-1:0] s7_sel_o;
output s7_we_o;
output s7_cyc_o;
output s7_stb_o;
output s7_cab_o;
input s7_ack_i;
input s7_err_i;
input s7_rty_i;
// Slave 8 Interface
input [`dw-1:0] s8_dat_i;
output [`dw-1:0] s8_dat_o;
output [`aw-1:0] s8_adr_o;
output [`sw-1:0] s8_sel_o;
output s8_we_o;
output s8_cyc_o;
output s8_stb_o;
output s8_cab_o;
input s8_ack_i;
input s8_err_i;
input s8_rty_i;
// Slave 9 Interface
input [`dw-1:0] s9_dat_i;
output [`dw-1:0] s9_dat_o;
output [`aw-1:0] s9_adr_o;
output [`sw-1:0] s9_sel_o;
output s9_we_o;
output s9_cyc_o;
output s9_stb_o;
output s9_cab_o;
input s9_ack_i;
input s9_err_i;
input s9_rty_i;
// Slave 10 Interface
input [`dw-1:0] s10_dat_i;
output [`dw-1:0] s10_dat_o;
output [`aw-1:0] s10_adr_o;
output [`sw-1:0] s10_sel_o;
output s10_we_o;
output s10_cyc_o;
output s10_stb_o;
output s10_cab_o;
input s10_ack_i;
input s10_err_i;
input s10_rty_i;
// Slave 11 Interface
input [`dw-1:0] s11_dat_i;
output [`dw-1:0] s11_dat_o;
output [`aw-1:0] s11_adr_o;
output [`sw-1:0] s11_sel_o;
output s11_we_o;
output s11_cyc_o;
output s11_stb_o;
output s11_cab_o;
input s11_ack_i;
input s11_err_i;
input s11_rty_i;
// Slave 12 Interface
input [`dw-1:0] s12_dat_i;
output [`dw-1:0] s12_dat_o;
output [`aw-1:0] s12_adr_o;
output [`sw-1:0] s12_sel_o;
output s12_we_o;
output s12_cyc_o;
output s12_stb_o;
output s12_cab_o;
input s12_ack_i;
input s12_err_i;
input s12_rty_i;
// Slave 13 Interface
input [`dw-1:0] s13_dat_i;
output [`dw-1:0] s13_dat_o;
output [`aw-1:0] s13_adr_o;
output [`sw-1:0] s13_sel_o;
output s13_we_o;
output s13_cyc_o;
output s13_stb_o;
output s13_cab_o;
input s13_ack_i;
input s13_err_i;
input s13_rty_i;
// Slave 14 Interface
input [`dw-1:0] s14_dat_i;
output [`dw-1:0] s14_dat_o;
output [`aw-1:0] s14_adr_o;
output [`sw-1:0] s14_sel_o;
output s14_we_o;
output s14_cyc_o;
output s14_stb_o;
output s14_cab_o;
input s14_ack_i;
input s14_err_i;
input s14_rty_i;
// Slave 15 Interface
input [`dw-1:0] s15_dat_i;
output [`dw-1:0] s15_dat_o;
output [`aw-1:0] s15_adr_o;
output [`sw-1:0] s15_sel_o;
output s15_we_o;
output s15_cyc_o;
output s15_stb_o;
output s15_cab_o;
input s15_ack_i;
input s15_err_i;
input s15_rty_i;
////////////////////////////////////////////////////////////////////
//
// Local wires
//
wire [`mselectw -1:0] i_gnt_arb;
wire [2:0] gnt;
reg [`sselectw -1:0] i_ssel_dec;
`ifdef WB_USE_TRISTATE
wire [`mbusw -1:0] i_bus_m;
`else
reg [`mbusw -1:0] i_bus_m; // internal share bus, master data and control to slave
`endif
wire [`dw -1:0] i_dat_s; // internal share bus , slave data to master
wire [`sbusw -1:0] i_bus_s; // internal share bus , slave control to master
////////////////////////////////////////////////////////////////////
//
// Master output Interfaces
//
// master0
assign m0_dat_o = i_dat_s;
assign {m0_ack_o, m0_err_o, m0_rty_o} = i_bus_s & {3{i_gnt_arb[0]}};
// master1
assign m1_dat_o = i_dat_s;
assign {m1_ack_o, m1_err_o, m1_rty_o} = i_bus_s & {3{i_gnt_arb[1]}};
// master2
assign m2_dat_o = i_dat_s;
assign {m2_ack_o, m2_err_o, m2_rty_o} = i_bus_s & {3{i_gnt_arb[2]}};
// master3
assign m3_dat_o = i_dat_s;
assign {m3_ack_o, m3_err_o, m3_rty_o} = i_bus_s & {3{i_gnt_arb[3]}};
// master4
assign m4_dat_o = i_dat_s;
assign {m4_ack_o, m4_err_o, m4_rty_o} = i_bus_s & {3{i_gnt_arb[4]}};
// master5
assign m5_dat_o = i_dat_s;
assign {m5_ack_o, m5_err_o, m5_rty_o} = i_bus_s & {3{i_gnt_arb[5]}};
// master6
assign m6_dat_o = i_dat_s;
assign {m6_ack_o, m6_err_o, m6_rty_o} = i_bus_s & {3{i_gnt_arb[6]}};
// master7
assign m7_dat_o = i_dat_s;
assign {m7_ack_o, m7_err_o, m7_rty_o} = i_bus_s & {3{i_gnt_arb[7]}};
// mounthorse begin
//assign i_bus_s = {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i ,
// s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i ,
// s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i };
reg bushole;
assign i_bus_s = bushole ? 3'b010 : {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i | s8_ack_i | s9_ack_i | s10_ack_i | s11_ack_i | s12_ack_i | s13_ack_i | s14_ack_i | s15_ack_i ,
s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i | s8_err_i | s9_err_i | s10_err_i | s11_err_i | s12_err_i | s13_err_i | s14_err_i | s15_err_i ,
s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i | s8_rty_i | s9_rty_i | s10_rty_i | s11_rty_i | s12_rty_i | s13_rty_i | s14_rty_i | s15_rty_i};
// mounthorse end
////////////////////////////////
// Slave output interface
//
// slave0
assign {s0_adr_o, s0_sel_o, s0_dat_o, s0_we_o, s0_cab_o,s0_cyc_o} = i_bus_m[`mbusw -1:1];
assign s0_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[0]; // stb_o = cyc_i & stb_i & i_ssel_dec
// slave1
assign {s1_adr_o, s1_sel_o, s1_dat_o, s1_we_o, s1_cab_o, s1_cyc_o} = i_bus_m[`mbusw -1:1];
assign s1_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[1];
// slave2
assign {s2_adr_o, s2_sel_o, s2_dat_o, s2_we_o, s2_cab_o, s2_cyc_o} = i_bus_m[`mbusw -1:1];
assign s2_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[2];
// slave3
assign {s3_adr_o, s3_sel_o, s3_dat_o, s3_we_o, s3_cab_o, s3_cyc_o} = i_bus_m[`mbusw -1:1];
assign s3_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[3];
// slave4
assign {s4_adr_o, s4_sel_o, s4_dat_o, s4_we_o, s4_cab_o, s4_cyc_o} = i_bus_m[`mbusw -1:1];
assign s4_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[4];
// slave5
assign {s5_adr_o, s5_sel_o, s5_dat_o, s5_we_o, s5_cab_o, s5_cyc_o} = i_bus_m[`mbusw -1:1];
assign s5_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[5];
// slave6
assign {s6_adr_o, s6_sel_o, s6_dat_o, s6_we_o, s6_cab_o, s6_cyc_o} = i_bus_m[`mbusw -1:1];
assign s6_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[6];
// slave7
assign {s7_adr_o, s7_sel_o, s7_dat_o, s7_we_o, s7_cab_o, s7_cyc_o} = i_bus_m[`mbusw -1:1];
assign s7_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[7];
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