📄 wb_conbusex_top.v
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/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Connection Bus Top Level ////
//// ////
//// ////
//// Author: Johny Chi ////
//// chisuhua@yahoo.com.cn ////
//// ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//
// 1.8 masters and 8 slaves share bus Wishbone connection
// 2.no priorty arbitor , 8 masters are processed in a round
// robin way,
// 3.if WB_USE_TRISTATE was defined, the share bus is a tristate
// bus, and use less logic resource.
// 4.wb_conbus was synthesis to XC2S100-5-PQ208 using synplify,
// Max speed >60M , and 374 SLICE if using Multiplexor bus
// or 150 SLICE if using tri-state bus.
//
`include "timescale.v"
`define dw 32 // Data bus Width
`define aw 32 // Address bus Width
`define sw `dw / 8 // Number of Select Lines
`define mbusw `aw + `sw + `dw +4 //address width + byte select width + dat width + cyc + we + stb +cab , input from master interface
`define sbusw 3 // ack + err + rty, input from slave interface
`define mselectw 8 // number of masters
`define sselectw 16 // number of slavers
//`define WB_USE_TRISTATE
module wb_conbusex_top(
clk_i, rst_i,
// Master 0 Interface
m0_dat_i, m0_dat_o, m0_adr_i, m0_sel_i, m0_we_i, m0_cyc_i,
m0_stb_i, m0_ack_o, m0_err_o, m0_rty_o, m0_cab_i,
// Master 1 Interface
m1_dat_i, m1_dat_o, m1_adr_i, m1_sel_i, m1_we_i, m1_cyc_i,
m1_stb_i, m1_ack_o, m1_err_o, m1_rty_o, m1_cab_i,
// Master 2 Interface
m2_dat_i, m2_dat_o, m2_adr_i, m2_sel_i, m2_we_i, m2_cyc_i,
m2_stb_i, m2_ack_o, m2_err_o, m2_rty_o, m2_cab_i,
// Master 3 Interface
m3_dat_i, m3_dat_o, m3_adr_i, m3_sel_i, m3_we_i, m3_cyc_i,
m3_stb_i, m3_ack_o, m3_err_o, m3_rty_o, m3_cab_i,
// Master 4 Interface
m4_dat_i, m4_dat_o, m4_adr_i, m4_sel_i, m4_we_i, m4_cyc_i,
m4_stb_i, m4_ack_o, m4_err_o, m4_rty_o, m4_cab_i,
// Master 5 Interface
m5_dat_i, m5_dat_o, m5_adr_i, m5_sel_i, m5_we_i, m5_cyc_i,
m5_stb_i, m5_ack_o, m5_err_o, m5_rty_o, m5_cab_i,
// Master 6 Interface
m6_dat_i, m6_dat_o, m6_adr_i, m6_sel_i, m6_we_i, m6_cyc_i,
m6_stb_i, m6_ack_o, m6_err_o, m6_rty_o, m6_cab_i,
// Master 7 Interface
m7_dat_i, m7_dat_o, m7_adr_i, m7_sel_i, m7_we_i, m7_cyc_i,
m7_stb_i, m7_ack_o, m7_err_o, m7_rty_o, m7_cab_i,
// Slave 0 Interface
s0_dat_i, s0_dat_o, s0_adr_o, s0_sel_o, s0_we_o, s0_cyc_o,
s0_stb_o, s0_ack_i, s0_err_i, s0_rty_i, s0_cab_o,
// Slave 1 Interface
s1_dat_i, s1_dat_o, s1_adr_o, s1_sel_o, s1_we_o, s1_cyc_o,
s1_stb_o, s1_ack_i, s1_err_i, s1_rty_i, s1_cab_o,
// Slave 2 Interface
s2_dat_i, s2_dat_o, s2_adr_o, s2_sel_o, s2_we_o, s2_cyc_o,
s2_stb_o, s2_ack_i, s2_err_i, s2_rty_i, s2_cab_o,
// Slave 3 Interface
s3_dat_i, s3_dat_o, s3_adr_o, s3_sel_o, s3_we_o, s3_cyc_o,
s3_stb_o, s3_ack_i, s3_err_i, s3_rty_i, s3_cab_o,
// Slave 4 Interface
s4_dat_i, s4_dat_o, s4_adr_o, s4_sel_o, s4_we_o, s4_cyc_o,
s4_stb_o, s4_ack_i, s4_err_i, s4_rty_i, s4_cab_o,
// Slave 5 Interface
s5_dat_i, s5_dat_o, s5_adr_o, s5_sel_o, s5_we_o, s5_cyc_o,
s5_stb_o, s5_ack_i, s5_err_i, s5_rty_i, s5_cab_o,
// Slave 6 Interface
s6_dat_i, s6_dat_o, s6_adr_o, s6_sel_o, s6_we_o, s6_cyc_o,
s6_stb_o, s6_ack_i, s6_err_i, s6_rty_i, s6_cab_o,
// Slave 7 Interface
s7_dat_i, s7_dat_o, s7_adr_o, s7_sel_o, s7_we_o, s7_cyc_o,
s7_stb_o, s7_ack_i, s7_err_i, s7_rty_i, s7_cab_o,
// Slave 8 Interface
s8_dat_i, s8_dat_o, s8_adr_o, s8_sel_o, s8_we_o, s8_cyc_o,
s8_stb_o, s8_ack_i, s8_err_i, s8_rty_i, s8_cab_o,
// Slave 9 Interface
s9_dat_i, s9_dat_o, s9_adr_o, s9_sel_o, s9_we_o, s9_cyc_o,
s9_stb_o, s9_ack_i, s9_err_i, s9_rty_i, s9_cab_o,
// Slave 10 Interface
s10_dat_i, s10_dat_o, s10_adr_o, s10_sel_o, s10_we_o, s10_cyc_o,
s10_stb_o, s10_ack_i, s10_err_i, s10_rty_i, s10_cab_o,
// Slave 11 Interface
s11_dat_i, s11_dat_o, s11_adr_o, s11_sel_o, s11_we_o, s11_cyc_o,
s11_stb_o, s11_ack_i, s11_err_i, s11_rty_i, s11_cab_o,
// Slave 12 Interface
s12_dat_i, s12_dat_o, s12_adr_o, s12_sel_o, s12_we_o, s12_cyc_o,
s12_stb_o, s12_ack_i, s12_err_i, s12_rty_i, s12_cab_o,
// Slave 13 Interface
s13_dat_i, s13_dat_o, s13_adr_o, s13_sel_o, s13_we_o, s13_cyc_o,
s13_stb_o, s13_ack_i, s13_err_i, s13_rty_i, s13_cab_o,
// Slave 14 Interface
s14_dat_i, s14_dat_o, s14_adr_o, s14_sel_o, s14_we_o, s14_cyc_o,
s14_stb_o, s14_ack_i, s14_err_i, s14_rty_i, s14_cab_o,
// Slave 15 Interface
s15_dat_i, s15_dat_o, s15_adr_o, s15_sel_o, s15_we_o, s15_cyc_o,
s15_stb_o, s15_ack_i, s15_err_i, s15_rty_i, s15_cab_o
);
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
parameter s0_addr_w = 3 ; // slave 0 address decode width
parameter s0_addr = 3'h0; // slave 0 address
parameter s1_addr_w = 3 ; // slave 1 address decode width
parameter s1_addr = 3'h1; // slave 1 address
parameter s2_addr_w = 8 ; // slave 2 address decode width
parameter s2_addr = 8'h90; // slave 2 address
parameter s3_addr_w = 8 ; // slave 3 address decode width
parameter s3_addr = 8'h91; // slave 3 address
parameter s4_addr_w = 8 ; // slave 4 address decode width
parameter s4_addr = 8'h92; // slave 4 address
parameter s5_addr_w = 8 ; // slave 5 address decode width
parameter s5_addr = 8'h93; // slave 5 address
parameter s6_addr_w = 8 ; // slave 6 address decode width
parameter s6_addr = 8'h94; // slave 6 address
parameter s7_addr_w = 8 ; // slave 7 address decode width
parameter s7_addr = 8'h95; // slave 7 address
parameter s8_addr_w = 8 ; // slave 8 address decode width
parameter s8_addr = 8'h96; // slave 8 address
parameter s9_addr_w = 8 ; // slave 9 address decode width
parameter s9_addr = 8'h97; // slave 9 address
parameter s10_addr_w = 8 ; // slave 10 address decode width
parameter s10_addr = 8'h98; // slave 10 address
parameter s11_addr_w = 8 ; // slave 11 address decode width
parameter s11_addr = 8'h99; // slave 11 address
parameter s12_addr_w = 8 ; // slave 12 address decode width
parameter s12_addr = 8'h9a; // slave 12 address
parameter s13_addr_w = 8 ; // slave 13 address decode width
parameter s13_addr = 8'h9b; // slave 13 address
parameter s14_addr_w = 8 ; // slave 14 address decode width
parameter s14_addr = 8'h9c; // slave 14 address
parameter s15_addr_w = 8 ; // slave 15 address decode width
parameter s15_addr = 8'h9d; // slave 15 address
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input clk_i, rst_i;
// Master 0 Interface
input [`dw-1:0] m0_dat_i;
output [`dw-1:0] m0_dat_o;
input [`aw-1:0] m0_adr_i;
input [`sw-1:0] m0_sel_i;
input m0_we_i;
input m0_cyc_i;
input m0_stb_i;
input m0_cab_i;
output m0_ack_o;
output m0_err_o;
output m0_rty_o;
// Master 1 Interface
input [`dw-1:0] m1_dat_i;
output [`dw-1:0] m1_dat_o;
input [`aw-1:0] m1_adr_i;
input [`sw-1:0] m1_sel_i;
input m1_we_i;
input m1_cyc_i;
input m1_stb_i;
input m1_cab_i;
output m1_ack_o;
output m1_err_o;
output m1_rty_o;
// Master 2 Interface
input [`dw-1:0] m2_dat_i;
output [`dw-1:0] m2_dat_o;
input [`aw-1:0] m2_adr_i;
input [`sw-1:0] m2_sel_i;
input m2_we_i;
input m2_cyc_i;
input m2_stb_i;
input m2_cab_i;
output m2_ack_o;
output m2_err_o;
output m2_rty_o;
// Master 3 Interface
input [`dw-1:0] m3_dat_i;
output [`dw-1:0] m3_dat_o;
input [`aw-1:0] m3_adr_i;
input [`sw-1:0] m3_sel_i;
input m3_we_i;
input m3_cyc_i;
input m3_stb_i;
input m3_cab_i;
output m3_ack_o;
output m3_err_o;
output m3_rty_o;
// Master 4 Interface
input [`dw-1:0] m4_dat_i;
output [`dw-1:0] m4_dat_o;
input [`aw-1:0] m4_adr_i;
input [`sw-1:0] m4_sel_i;
input m4_we_i;
input m4_cyc_i;
input m4_stb_i;
input m4_cab_i;
output m4_ack_o;
output m4_err_o;
output m4_rty_o;
// Master 5 Interface
input [`dw-1:0] m5_dat_i;
output [`dw-1:0] m5_dat_o;
input [`aw-1:0] m5_adr_i;
input [`sw-1:0] m5_sel_i;
input m5_we_i;
input m5_cyc_i;
input m5_stb_i;
input m5_cab_i;
output m5_ack_o;
output m5_err_o;
output m5_rty_o;
// Master 6 Interface
input [`dw-1:0] m6_dat_i;
output [`dw-1:0] m6_dat_o;
input [`aw-1:0] m6_adr_i;
input [`sw-1:0] m6_sel_i;
input m6_we_i;
input m6_cyc_i;
input m6_stb_i;
input m6_cab_i;
output m6_ack_o;
output m6_err_o;
output m6_rty_o;
// Master 7 Interface
input [`dw-1:0] m7_dat_i;
output [`dw-1:0] m7_dat_o;
input [`aw-1:0] m7_adr_i;
input [`sw-1:0] m7_sel_i;
input m7_we_i;
input m7_cyc_i;
input m7_stb_i;
input m7_cab_i;
output m7_ack_o;
output m7_err_o;
output m7_rty_o;
// Slave 0 Interface
input [`dw-1:0] s0_dat_i;
output [`dw-1:0] s0_dat_o;
output [`aw-1:0] s0_adr_o;
output [`sw-1:0] s0_sel_o;
output s0_we_o;
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