📄 lcd.rpt
字号:
Device: EP1K30QC208-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S V S S S S S S S S S S S S S V S S S S S S S S S S S S S S S S S S S S
E E E E E E E C E E E E E E V E E E E E E E C E V E E E E E E E E E E E V E E E E E E E E
R R R R R R R C R R R R R R C R R R R R R R C R C R R R R R R R R R R R C R R R R R R R R
V V V V V V V I V V V V V V C V V V V V G V V I G G G G r V C V V V V V V G V V V V V C V V V V V V V V
E E E E E E E N E E E E E E I E E E E E N E E N N N N N s E I E E E E E E N E E E E E I E E E E E E E E
D D D D D D D T D D D D D D O D D D D D D D D T D D D D t D O D D D D D D D D D D D D O D D D D D D D D
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | VCCINT
GND | 6 151 | GND
RESERVED | 7 150 | RESERVED
RESERVED | 8 149 | RESERVED
RESERVED | 9 148 | RESERVED
RESERVED | 10 147 | RESERVED
RESERVED | 11 146 | VCCIO
RESERVED | 12 145 | GND
RESERVED | 13 144 | RESERVED
RESERVED | 14 143 | RESERVED
RESERVED | 15 142 | RESERVED
RESERVED | 16 141 | RESERVED
RESERVED | 17 140 | RESERVED
RESERVED | 18 139 | rs
RESERVED | 19 138 | VCCIO
GND | 20 137 | GND
VCCINT | 21 136 | e
VCCIO | 22 135 | rw
GND | 23 134 | db1
RESERVED | 24 133 | db0
RESERVED | 25 132 | db3
RESERVED | 26 131 | db2
RESERVED | 27 EP1K30QC208-3 130 | VCCINT
RESERVED | 28 129 | GND
RESERVED | 29 128 | db5
RESERVED | 30 127 | db4
RESERVED | 31 126 | db7
GND | 32 125 | db6
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | cs2
RESERVED | 36 121 | cs1
RESERVED | 37 120 | RESERVED
RESERVED | 38 119 | rstb
RESERVED | 39 118 | VCCIO
RESERVED | 40 117 | GND
RESERVED | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
GND | 43 114 | RESERVED
RESERVED | 44 113 | RESERVED
RESERVED | 45 112 | RESERVED
RESERVED | 46 111 | RESERVED
RESERVED | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R R R R R G R R R R R R V R R R R R V R R R G V G c G G G R V R R R R R R V R R R R R R V R R R R R R
E E E E E E N E E E E E E C E E E E E C E E E N C N l N N N E C E E E E E E C E E E E E E C E E E E E E
S S S S S S D S S S S S S C S S S S S C S S S D C D k D D D S C S S S S S S C S S S S S S C S S S S S S
E E E E E E E E E E E E I E E E E E I E E E I E I E E E E E E I E E E E E E I E E E E E E
R R R R R R R R R R R R O R R R R R N R R R N R O R R R R R R N R R R R R R O R R R R R R
V V V V V V V V V V V V V V V V V T V V V T V V V V V V V T V V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information:f:\work\fpga_platform\fpga_evm\20041113\lcd_max\lcd_max_wrapper\lcd.rpt
lcd
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 0/2 0/2 16/22( 72%)
A2 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 15/22( 68%)
A3 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 18/22( 81%)
A4 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 19/22( 86%)
A5 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 16/22( 72%)
A6 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 17/22( 77%)
A7 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 0/2 0/2 11/22( 50%)
A8 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 18/22( 81%)
A9 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 0/2 0/2 14/22( 63%)
A10 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 15/22( 68%)
A11 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
A12 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 19/22( 86%)
A13 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 17/22( 77%)
A14 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
A15 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 16/22( 72%)
A16 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 15/22( 68%)
A17 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 15/22( 68%)
A18 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 17/22( 77%)
A19 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 18/22( 81%)
A20 5/ 8( 62%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
A21 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 19/22( 86%)
A22 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 1/2 16/22( 72%)
A23 6/ 8( 75%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 17/22( 77%)
A24 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 18/22( 81%)
A25 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 16/22( 72%)
A26 4/ 8( 50%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
A27 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 13/22( 59%)
A28 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 20/22( 90%)
A29 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 13/22( 59%)
A30 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 17/22( 77%)
A31 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 14/22( 63%)
A32 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 16/22( 72%)
A33 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
A34 8/ 8(100%) 4/ 8( 50%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
A35 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 18/22( 81%)
A36 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 20/22( 90%)
B1 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
B2 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 19/22( 86%)
B5 1/ 8( 12%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B6 5/ 8( 62%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
B7 1/ 8( 12%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B8 8/ 8(100%) 6/ 8( 75%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
B9 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
B10 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
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