lcd.rpt

这是一个用ALTER公司FPGA控制外部128×64液晶的程序

Project Informationf:\work\fpga_platform\fpga_evm\20041113\lcd_max\lcd_max_wrapper\lcd.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 12/06/2004 22:15:21

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

lcd       EP1K30QC208-3    2      14     0    0         0  %    578      33 %

User Pins:                 2      14     0  



Project Informationf:\work\fpga_platform\fpga_evm\20041113\lcd_max\lcd_max_wrapper\lcd.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Flipflop '|lcd0:2|lcd_ctrl:TLC5615|:242' stuck at GND


** PROJECT TIMING MESSAGES **

Warning: Timing characteristics of device EP1K30QC208-3 are preliminary


Project Informationf:\work\fpga_platform\fpga_evm\20041113\lcd_max\lcd_max_wrapper\lcd.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

lcd@79                            clk
lcd@121                           cs1
lcd@122                           cs2
lcd@133                           db0
lcd@134                           db1
lcd@131                           db2
lcd@132                           db3
lcd@127                           db4
lcd@128                           db5
lcd@125                           db6
lcd@126                           db7
lcd@136                           e
lcd@139                           rs
lcd@180                           rst
lcd@119                           rstb
lcd@135                           rw


Project Informationf:\work\fpga_platform\fpga_evm\20041113\lcd_max\lcd_max_wrapper\lcd.rpt

** FILE HIERARCHY **



|lcd0:2|
|lcd0:2|lpm_add_sub:170|
|lcd0:2|lpm_add_sub:170|addcore:adder|
|lcd0:2|lpm_add_sub:170|altshift:result_ext_latency_ffs|
|lcd0:2|lpm_add_sub:170|altshift:carry_ext_latency_ffs|
|lcd0:2|lpm_add_sub:170|altshift:oflow_ext_latency_ffs|
|lcd0:2|lpm_add_sub:171|
|lcd0:2|lpm_add_sub:171|addcore:adder|
|lcd0:2|lpm_add_sub:171|altshift:result_ext_latency_ffs|
|lcd0:2|lpm_add_sub:171|altshift:carry_ext_latency_ffs|
|lcd0:2|lpm_add_sub:171|altshift:oflow_ext_latency_ffs|
|lcd0:2|lcd_ctrl:TLC5615|
|lcd0:2|lcd_ctrl:TLC5615|lpm_add_sub:294|
|lcd0:2|lcd_ctrl:TLC5615|lpm_add_sub:294|addcore:adder|
|lcd0:2|lcd_ctrl:TLC5615|lpm_add_sub:294|altshift:result_ext_latency_ffs|
|lcd0:2|lcd_ctrl:TLC5615|lpm_add_sub:294|altshift:carry_ext_latency_ffs|
|lcd0:2|lcd_ctrl:TLC5615|lpm_add_sub:294|altshift:oflow_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1033|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1033|addcore:adder|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1033|altshift:result_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1033|altshift:carry_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1033|altshift:oflow_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1034|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1034|addcore:adder|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1034|altshift:result_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1034|altshift:carry_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1034|altshift:oflow_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1035|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1035|addcore:adder|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1035|altshift:result_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1035|altshift:carry_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1035|altshift:oflow_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1036|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1036|addcore:adder|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1036|altshift:result_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1036|altshift:carry_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1036|altshift:oflow_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1037|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1037|addcore:adder|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1037|altshift:result_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1037|altshift:carry_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1037|altshift:oflow_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1038|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1038|addcore:adder|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1038|altshift:result_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1038|altshift:carry_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1038|altshift:oflow_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1039|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1039|addcore:adder|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1039|altshift:result_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1039|altshift:carry_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1039|altshift:oflow_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1040|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1040|addcore:adder|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1040|altshift:result_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1040|altshift:carry_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1040|altshift:oflow_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1041|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1041|addcore:adder|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1041|altshift:result_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1041|altshift:carry_ext_latency_ffs|
|lcd0:2|lcd_init:LCD|lpm_add_sub:1041|altshift:oflow_ext_latency_ffs|
|lcd0:2|data_rom:ROM|


Device-Specific Information:f:\work\fpga_platform\fpga_evm\20041113\lcd_max\lcd_max_wrapper\lcd.rpt
lcd

***** Logic for device 'lcd' compiled without errors.