lcd0.v

这是一个用ALTER公司FPGA控制外部128×64液晶的程序

module lcd0(clk,rst,E,CS1,CS2,RS,RW,DB,RSTB  );
input clk,rst;
output RSTB,CS1,CS2,RS,RW,E;
output [7:0] DB;

reg  [7:0]cter8;
reg  [2:0]state_cter;
reg  clk8_d,clk8;

wire [1:0]cs;
wire [7:0]data,wr_data;
wire [9:0]data_addr;
//wire  rsp;
wire rs;
wire RSTB,CS1,CS2,RS,RW,E;
wire  [7:0] DB;
always @ (posedge clk or posedge rst)
         if(rst) cter8<=8'h00;
         else if(cter8<8'h3f) cter8<=cter8+1'b1;
         else if(cter8==8'h3f) cter8<=8'h00;
         else cter8<=cter8;

always @ (posedge clk or posedge rst)
         if(rst) clk8<=1'b0;
         else clk8<=cter8[5];

always @ (posedge clk or posedge rst)
         if(rst) clk8_d<=1'b0;
         else clk8_d<=clk8;

wire     clk8_r=clk8 & ~clk8_d;
wire     clk8_f=~clk8 & clk8_d;

always @ (posedge clk or posedge rst)
         if(rst) state_cter<=3'b000;
         else if(clk8_r && state_cter<3'b111) state_cter<=state_cter+1'b1;
         else if(clk8_r && state_cter==3'b111) state_cter<=3'b000;
         else state_cter<=state_cter;

lcd_ctrl TLC5615(clk,rst,state_cter,clk8_f,clk8_r,cs,rs,data,RSTB,E,CS1,CS2,RS,RW,DB);
lcd_init LCD(clk,rst,state_cter,clk8_r,clk8_f,RSTB,cs,rs,data,data_addr,wr_data);
data_rom ROM(data_addr,wr_data,clk);

endmodule

module lcd_init(clk,rst,cter8,clk8_r,clk8_f,RSTB,cs,rs,data,data_addr,wr_data);
input clk,rst;
input [2:0] cter8;
input [7:0] wr_data;
input clk8_r,clk8_f;
input RSTB;

output rs;
output[1:0] cs;
//output[1:0] state;
output[7:0] data;
output[9:0] data_addr;


reg rs;
reg[1:0] cs;
reg[7:0] data;

reg[9:0] data_addr;

reg[7:0] data_reg;
reg[1:0] cs_reg;
reg rs_reg;
reg type;

reg [1:0]state;
//0:no initializing,1:rstb singal setting,2:display on/off and display start line setting,3:clear screen

reg tcter;
reg  cscter;
reg [5:0] ycter;
reg [2:0] xcter;

always @ (posedge clk or posedge rst)
         if(rst) state<=2'h0;
         else if(RSTB && state==2'h0 && !type && tcter && cscter && clk8_f && cter8[1:0]==2'h3) state<=2'h1;
         else if(RSTB && state==2'h1 && type && xcter==3'h7 && cscter && ycter==6'h00 && clk8_f && cter8[1:0]==2'h3) state<=2'h2;
         else if(RSTB && state==2'h2 && type && xcter==3'h7 && cscter && ycter==6'h00 && clk8_f && cter8[1:0]==2'h3) state<=2'h2;
         else state<=state;
         
always @ (posedge clk or posedge rst)
         if(rst) type<=1'b0;
         else if(RSTB && (state==2'h1 || state==2'h2) && !type && tcter && cscter && clk8_f && cter8[1:0]==2'h3) type<=1'b1;
         else if(RSTB && state==2'h1 && type && cscter && ycter==6'h00 && clk8_f && cter8[1:0]==2'h3) type<=1'b0; 
         else if(RSTB && state==2'h2 && type && cscter && ycter==6'h00 && clk8_f && cter8[1:0]==2'h3) type<=1'b0;
         else type<=type;
         
always @ (posedge clk or posedge rst)
         if(rst) tcter<=1'b0;
         else if(RSTB && state==2'h0 && !type && !tcter && clk8_f && cter8[1:0]==2'h3) tcter<=tcter+1'b1;
         else if(RSTB && state==2'h0 && !type && tcter && clk8_f && cter8[1:0]==2'h3) tcter<=1'b0;
         else if(RSTB && (state==2'h1 || state==2'h2) && !type && !tcter && clk8_f && cter8[1:0]==2'h3) tcter<=tcter+1'b1;
         else if(RSTB && (state==2'h1 || state==2'h2) && !type && tcter && clk8_f && cter8[1:0]==2'h3) tcter<=1'b0; 
         else tcter<=tcter;
         
always @ (posedge clk or posedge rst)
         if(rst) ycter<=6'h3f;
         else if(RSTB && (state==2'h1 || state==2'h2) && type && ycter>6'h00 && clk8_f && cter8[1:0]==2'h3) ycter<=ycter-6'h01;
         else if(RSTB && (state==2'h1 || state==2'h2) && type && ycter==6'h00 && clk8_f && cter8[1:0]==2'h3) ycter<=6'h3f; 
         else ycter<=ycter;
         
always @ (posedge clk or posedge rst)
         if(rst) cscter<=1'b0;
         else if(RSTB && state==2'h0 && !type && !cscter && tcter && clk8_f && cter8[1:0]==2'h3) cscter<=cscter+1'b1;
         else if(RSTB && state==2'h0 && !type && cscter && tcter && clk8_f && cter8[1:0]==2'h3) cscter<=1'b0;
         else if(RSTB && (state==2'h1 || state==2'h2) && !type && !cscter && tcter && clk8_f && cter8[1:0]==2'h3) cscter<=cscter+1'b1;
         else if(RSTB && (state==2'h1 || state==2'h2) && !type && cscter && tcter && clk8_f && cter8[1:0]==2'h3) cscter<=1'b0;
         else if(RSTB && (state==2'h1 || state==2'h2) && type && ycter==6'h00 && !cscter && clk8_f && cter8[1:0]==2'h3) cscter<=cscter+1'b1;
         else if(RSTB && (state==2'h1 || state==2'h2) && type && ycter==6'h00 && cscter && clk8_f && cter8[1:0]==2'h3) cscter<=1'b0; 
         else cscter<=cscter;

always @ (posedge clk or posedge rst)
         if(rst) xcter<=3'h0;
         else if(RSTB && state==2'h1 && type && ycter==6'h00 && cscter && xcter<3'h7 && clk8_f && cter8[1:0]==2'h3) xcter<=xcter+3'h1;
         else if(RSTB && state==2'h1 && type && ycter==6'h00 && cscter && xcter==3'h7 && clk8_f && cter8[1:0]==2'h3) xcter<=3'h0; 
         else if(RSTB && state==2'h2 && type && ycter==6'h00 && cscter && xcter<3'h7 && clk8_f && cter8[1:0]==2'h3) xcter<=xcter+3'h1;
         else if(RSTB && state==2'h2 && type && ycter==6'h00 && cscter && xcter==3'h7 && clk8_f && cter8[1:0]==2'h3) xcter<=3'h0; 
         else xcter<=xcter;
         
always @ (posedge clk or posedge rst)
         if(rst) data_reg<=8'h00;
         else if(RSTB && state==2'h0 && !type && !tcter && clk8_f && cter8[1:0]==2'h2) data_reg<=8'h3f;
         else if(RSTB && state==2'h0 && !type && tcter && clk8_f && cter8[1:0]==2'h2) data_reg<=8'hc0; 
         else if(RSTB && (state==2'h1 || state==2'h2) && !type && !tcter && clk8_f && cter8[1:0]==2'h2) data_reg<=8'h40;
         else if(RSTB && (state==2'h1 || state==2'h2) && !type && tcter && clk8_f && cter8[1:0]==2'h2) data_reg<={5'b10111,xcter};
         else if(RSTB && state==2'h1 && type && clk8_f && cter8[1:0]==2'h2) data_reg<=8'h00;
         else if(RSTB && state==2'h2 && type && clk8_f && cter8[1:0]==2'h2) data_reg<=wr_data;
         else data_reg<=data_reg;
         
always @ (posedge clk or posedge rst)
         if(rst) cs_reg<=2'h3;
         else if(RSTB && (state==2'h0 ||state==2'h1 || state==2'h2) && !cscter && clk8_r && cter8[1:0]==2'h2) cs_reg<=2'h1;
         else if(RSTB && (state==2'h0 ||state==2'h1 || state==2'h2) && cscter && clk8_r && cter8[1:0]==2'h2) cs_reg<=2'h2;
         else cs_reg<=cs_reg;         
         
always @ (posedge clk or posedge rst)
         if(rst) rs_reg<=1'b0;
         else if(RSTB && clk8_r && cter8[1:0]==2'h2) rs_reg<=type;
         else rs_reg<=rs_reg; 

always @ (posedge clk or posedge rst)
         if(rst) data_addr<=10'h000;
         else if(RSTB && state==2'h2 && type && clk8_r && cter8[1:0]==2'h2) data_addr<={(3'h7-xcter),!cscter,ycter};
         else data_addr<=data_addr;       

always @ (posedge clk or posedge rst)
         if(rst) rs<=1'b0;
         else if(RSTB && clk8_f && cter8[1:0]==2'h3) rs<=rs_reg;
         else rs<=rs;       
             
always @ (posedge clk or posedge rst)
         if(rst) data<=8'h00;
         else if(RSTB && clk8_f && cter8[1:0]==2'h3) data<=data_reg;
         else data<=data;       

always @ (posedge clk or posedge rst)
         if(rst) cs<=2'h3;
         else if(RSTB && clk8_f && cter8[1:0]==2'h3) cs<=cs_reg;
         else cs<=cs;  


 
endmodule

module lcd_ctrl(clk,rst,cter8,clk8_f,clk8_r,cs,rs,data,RSTB,E,
    CSL,
    CSR,
    A0,
    RW,DB);
input clk,rst;
input clk8_r,clk8_f;
input [2:0]cter8;
input rs;
input [1:0]cs;
input [7:0]data;
output RSTB,
  CSL,
  CSR,
  A0,
  RW,E;
output[7:0] DB;


reg reg_rs;
reg [1:0] reg_cs;
reg [7:0] reg_data;
reg 
 CSL,
 CSR,
 A0,
 RW,E,RSTB;
reg[7:0] DB;
reg [5:0]rstcter;



always @ (posedge clk or posedge rst)
         if(rst) reg_cs<=2'h3;
         else if((!cs[1] || !cs[0]) && clk8_r && cter8[1:0]==2'h3) reg_cs<=cs;
         else reg_cs<=reg_cs;
         
always @ (posedge clk or posedge rst)
         if(rst) reg_rs<=1'h0;
         else if((!cs[1] || !cs[0]) && clk8_r && cter8[1:0]==2'h3) reg_rs<=rs;
         else reg_rs<=reg_rs;
                  
always @ (posedge clk or posedge rst)
         if(rst) reg_data<=8'h00;
         else if((!cs[1] || !cs[0]) && clk8_r && cter8[1:0]==2'h3) reg_data<=data;
         else reg_data<=reg_data;
         
//RSTB SINGAL SETTING
always @ (posedge clk or posedge rst)
         if(rst) RSTB<=1'b0;
         else if(rstcter==6'h3f) RSTB<=1'b1;
         else RSTB<=RSTB;
         
always @ (posedge clk or posedge rst)
         if(rst) rstcter<=6'h00;
         else if(!RSTB && rstcter<6'h3f) rstcter<=rstcter+1'b1;
         else if(!RSTB && rstcter==6'h3f)  rstcter<=6'h3f;
         else rstcter<=rstcter;       

always @ (posedge clk or posedge rst)
         if(rst)CSL<=1'b1;
         else if((!reg_cs[1] || !reg_cs[0]) && RSTB && cter8[1:0]==2'h0 && clk8_f ) CSL<=reg_cs[0];
         else if((!reg_cs[1] || !reg_cs[0]) && RSTB && cter8[1:0]==2'h3 && clk8_f ) CSL<=1'b1;
         else CSL<=CSL;
         
always @ (posedge clk or posedge rst)
         if(rst)CSR<=1'b1;
         else if((!reg_cs[1] || !reg_cs[0]) && RSTB && cter8[1:0]==2'h0 && clk8_f )CSR<=reg_cs[1];
         else if((!reg_cs[1] || !reg_cs[0]) && RSTB && cter8[1:0]==2'h3 && clk8_f )CSR<=1'b1;
         else CSR<=CSR;

// e singal setting                 
always @ (posedge clk or posedge rst)
         if(rst) E<=1'b0; 
         else if((!reg_cs[1] || !reg_cs[0]) && RSTB && cter8[1:0]==2'h0 && clk8_r ) E<=1'b1;
         else if((!reg_cs[1] || !reg_cs[0]) && RSTB && cter8[1:0]==2'h2 && clk8_r ) E<=1'b0;
         else E<=E;

//DB singal setting
always @ (posedge clk or posedge rst)
         if(rst) DB<=8'h00;
         else if((!reg_cs[1] || !reg_cs[0]) && RSTB && cter8[1:0]==2'h0 && clk8_r) DB<=reg_data;
         else  DB<=DB ;

//rs singal setting
always @ (posedge clk or posedge rst) 
         if(rst) A0<=1'b1;
         else if((!reg_cs[1] || !reg_cs[0]) && RSTB && cter8[1:0]==2'h0 && clk8_f) A0<=reg_rs;
         else A0<=A0;

always @ (posedge clk or posedge rst) 
         if(rst) RW<=1'b0;
         else    RW<=1'b0;

endmodule 

module data_rom(addr,wr_data,clk);
input [9:0]  addr;
input        clk;
output [7:0] wr_data;
reg    [7:0] data;
wire  [7:0]wr_data={data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7]};
always@(posedge clk) begin
 
     case (addr) //" DIGITAL POWER  "
            10'h000:  data<=8'h00;//0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
           10'h001:  data<=8'h00;
           10'h002:  data<=8'h00;
           10'h003:  data<=8'h00;
           10'h004:  data<=8'h00;
           10'h005:  data<=8'h00;
           10'h006:  data<=8'h00;
           10'h007:  data<=8'h00;
           10'h008:  data<=8'h00;//0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
           10'h009:  data<=8'h00;
           10'h00a:  data<=8'h00;
           10'h00b:  data<=8'h00;
           10'h00c:  data<=8'h00;
           10'h00d:  data<=8'h00;
           10'h00e:  data<=8'h00;
           10'h00f:  data<=8'h00;
           10'h010:  data<=8'h00;//0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
           10'h011:  data<=8'h00;
           10'h012:  data<=8'h00;
           10'h013:  data<=8'h00;
           10'h014:  data<=8'h00;
           10'h015:  data<=8'h00;
           10'h016:  data<=8'h00;
           10'h017:  data<=8'h00;
           10'h018:  data<=8'h00;//0x00,0x00,0x00,0x00,0x00,0xE0,0x7E,0x7C,
           10'h019:  data<=8'h00;
           10'h01a:  data<=8'h00;
           10'h01b:  data<=8'h00;
           10'h01c:  data<=8'h00;
           10'h01d:  data<=8'he0;
           10'h01e:  data<=8'h7e;
           10'h01f:  data<=8'h7c;
           10'h020:  data<=8'he0;//0xE0,0x00,0x00,0x00,0x00,0x80,0x30,0x1C,
           10'h021:  data<=8'h00;
           10'h022:  data<=8'h00;
           10'h023:  data<=8'h00;
           10'h024:  data<=8'h00;
           10'h025:  data<=8'h80;
           10'h026:  data<=8'h30;
           10'h027:  data<=8'h1c;
           10'h028:  data<=8'hfe;//0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
           10'h029:  data<=8'h00;
           10'h02a:  data<=8'h00;
           10'h02b:  data<=8'h00;
           10'h02c:  data<=8'h00;
           10'h02d:  data<=8'h00;
           10'h02e:  data<=8'h00;
           10'h02f:  data<=8'h00;
           10'h030:  data<=8'h00;//0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
           10'h031:  data<=8'h00;
           10'h032:  data<=8'h00;
           10'h033:  data<=8'h00;
           10'h034:  data<=8'h00;